mirror of https://github.com/ARMmbed/mbed-os.git
135 lines
3.7 KiB
C
135 lines
3.7 KiB
C
/* mbed Microcontroller Library
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* Copyright (c) 2017 ARM Limited
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#if DEVICE_ITM
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#include "hal/itm_api.h"
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#include "cmsis.h"
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#include <stdbool.h>
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#ifndef ITM_STIM_FIFOREADY_Msk
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#define ITM_STIM_FIFOREADY_Msk 1
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#endif
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#define ITM_ENABLE_WRITE 0xC5ACCE55
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#define SWO_NRZ 0x02
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#define SWO_STIMULUS_PORT 0x01
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void mbed_itm_init(void)
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{
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static bool do_init = true;
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if (do_init) {
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do_init = false;
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itm_init();
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/* Enable write access to ITM registers. */
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ITM->LAR = ITM_ENABLE_WRITE;
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/* Trace Port Interface Selected Pin Protocol Register. */
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TPI->SPPR = (SWO_NRZ << TPI_SPPR_TXMODE_Pos);
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/* Trace Port Interface Formatter and Flush Control Register */
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TPI->FFCR = (1 << TPI_FFCR_TrigIn_Pos);
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/* Data Watchpoint and Trace Control Register */
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DWT->CTRL = (1 << DWT_CTRL_CYCTAP_Pos) |
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(0xF << DWT_CTRL_POSTINIT_Pos) |
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(0xF << DWT_CTRL_POSTPRESET_Pos) |
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(1 << DWT_CTRL_CYCCNTENA_Pos);
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/* Trace Privilege Register.
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* Disable access to trace channel configuration from non-privileged mode.
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*/
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ITM->TPR = 0x0;
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/* Trace Control Register */
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ITM->TCR = (1 << ITM_TCR_TraceBusID_Pos) |
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(1 << ITM_TCR_DWTENA_Pos) |
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(1 << ITM_TCR_SYNCENA_Pos) |
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(1 << ITM_TCR_ITMENA_Pos);
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/* Trace Enable Register */
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ITM->TER = SWO_STIMULUS_PORT;
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}
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}
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static void itm_out8(uint32_t port, uint8_t data)
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{
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/* Wait until port is available */
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while ((ITM->PORT[port].u32 & ITM_STIM_FIFOREADY_Msk) == 0) {
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__NOP();
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}
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/* write data to port */
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ITM->PORT[port].u8 = data;
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}
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static void itm_out32(uint32_t port, uint32_t data)
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{
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/* Wait until port is available */
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while ((ITM->PORT[port].u32 & ITM_STIM_FIFOREADY_Msk) == 0) {
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__NOP();
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}
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/* write data to port */
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ITM->PORT[port].u32 = data;
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}
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uint32_t mbed_itm_send(uint32_t port, uint32_t data)
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{
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/* Check if ITM and port is enabled */
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if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
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((ITM->TER & (1UL << port)) != 0UL)) { /* ITM Port enabled */
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itm_out32(port, data);
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}
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return data;
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}
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void mbed_itm_send_block(uint32_t port, const void *data, size_t len)
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{
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const char *ptr = data;
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/* Check if ITM and port is enabled */
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if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
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((ITM->TER & (1UL << port)) != 0UL)) { /* ITM Port enabled */
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/* Output single byte at a time until data is aligned */
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while ((((uintptr_t) ptr) & 3) && len != 0) {
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itm_out8(port, *ptr++);
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len--;
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}
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/* Output bulk of data one word at a time */
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while (len >= 4) {
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itm_out32(port, *(const uint32_t *) ptr);
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ptr += 4;
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len -= 4;
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}
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/* Output any trailing bytes */
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while (len != 0) {
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itm_out8(port, *ptr++);
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len--;
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}
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}
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}
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#endif // DEVICE_ITM
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