mirror of https://github.com/ARMmbed/mbed-os.git
317 lines
10 KiB
C
317 lines
10 KiB
C
/**************************************************************************//**
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* @file gic.h
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* @brief Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File
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* @version
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* @date 29 August 2013
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*
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* @note
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*
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******************************************************************************/
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/* Copyright (c) 2011 - 2013 ARM LIMITED
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name of ARM nor the names of its contributors may be used
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to endorse or promote products derived from this software without
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specific prior written permission.
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*
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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---------------------------------------------------------------------------*/
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#ifndef GIC_H_
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#define GIC_H_
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/* IO definitions (access restrictions to peripheral registers) */
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/**
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*/
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#ifdef __cplusplus
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#define __I volatile /*!< Defines 'read only' permissions */
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#else
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#define __I volatile const /*!< Defines 'read only' permissions */
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#endif
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#define __O volatile /*!< Defines 'write only' permissions */
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#define __IO volatile /*!< Defines 'read / write' permissions */
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/** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD)
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*/
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typedef struct
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{
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__IO uint32_t ICDDCR;
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__I uint32_t ICDICTR;
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__I uint32_t ICDIIDR;
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uint32_t RESERVED0[29];
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__IO uint32_t ICDISR[32];
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__IO uint32_t ICDISER[32];
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__IO uint32_t ICDICER[32];
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__IO uint32_t ICDISPR[32];
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__IO uint32_t ICDICPR[32];
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__I uint32_t ICDABR[32];
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uint32_t RESERVED1[32];
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__IO uint32_t ICDIPR[256];
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__IO uint32_t ICDIPTR[256];
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__IO uint32_t ICDICFR[64];
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uint32_t RESERVED2[128];
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__IO uint32_t ICDSGIR;
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} GICDistributor_Type;
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/** \brief Structure type to access the Controller Interface (GICC)
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*/
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typedef struct
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{
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__IO uint32_t ICCICR; // +0x000 - RW - CPU Interface Control Register
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__IO uint32_t ICCPMR; // +0x004 - RW - Interrupt Priority Mask Register
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__IO uint32_t ICCBPR; // +0x008 - RW - Binary Point Register
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__I uint32_t ICCIAR; // +0x00C - RO - Interrupt Acknowledge Register
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__IO uint32_t ICCEOIR; // +0x010 - WO - End of Interrupt Register
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__I uint32_t ICCRPR; // +0x014 - RO - Running Priority Register
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__I uint32_t ICCHPIR; // +0x018 - RO - Highest Pending Interrupt Register
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__IO uint32_t ICCABPR; // +0x01C - RW - Aliased Binary Point Register
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uint32_t RESERVED[55];
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__I uint32_t ICCIIDR; // +0x0FC - RO - CPU Interface Identification Register
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} GICInterface_Type;
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/*@} end of GICD */
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/* ########################## GIC functions #################################### */
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/** \brief Functions that manage interrupts via the GIC.
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@{
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*/
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/** \brief Enable DistributorGICInterface->ICCICR |= 1; //enable interface
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Enables the forwarding of pending interrupts to the CPU interfaces.
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*/
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void GIC_EnableDistributor(void);
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/** \brief Disable Distributor
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Disables the forwarding of pending interrupts to the CPU interfaces.
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*/
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void GIC_DisableDistributor(void);
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/** \brief Provides information about the configuration of the GIC.
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Provides information about the configuration of the GIC.
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- whether the GIC implements the Security Extensions
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- the maximum number of interrupt IDs that the GIC supports
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- the number of CPU interfaces implemented
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- if the GIC implements the Security Extensions, the maximum number of implemented Lockable Shared Peripheral Interrupts (LSPIs).
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\return Distributor Information.
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*/
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uint32_t GIC_DistributorInfo(void);
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/** \brief Distributor Implementer Identification Register.
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Distributor Implementer Identification Register
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\return Implementer Information.
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*/
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uint32_t GIC_DistributorImplementer(void);
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/** \brief Set list of processors that the interrupt is sent to if it is asserted.
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The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
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This field stores the list of processors that the interrupt is sent to if it is asserted.
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\param [in] IRQn Interrupt number.
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\param [in] target CPU target
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*/
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void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target);
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/** \brief Get list of processors that the interrupt is sent to if it is asserted.
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The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
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This field stores the list of processors that the interrupt is sent to if it is asserted.
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\param [in] IRQn Interrupt number.
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\param [in] target CPU target
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*/
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uint32_t GIC_GetTarget(IRQn_Type IRQn);
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/** \brief Enable Interface
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Enables the signalling of interrupts to the target processors.
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*/
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void GIC_EnableInterface(void);
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/** \brief Disable Interface
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Disables the signalling of interrupts to the target processors.
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*/
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void GIC_DisableInterface(void);
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/** \brief Acknowledge Interrupt
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The function acknowledges the highest priority pending interrupt and returns its IRQ number.
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\return Interrupt number
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*/
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IRQn_Type GIC_AcknowledgePending(void);
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/** \brief End Interrupt
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The function writes the end of interrupt register, indicating that handling of the interrupt is complete.
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\param [in] IRQn Interrupt number.
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*/
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void GIC_EndInterrupt(IRQn_Type IRQn);
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/** \brief Enable Interrupt
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Set-enable bit for each interrupt supported by the GIC.
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\param [in] IRQn External interrupt number.
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*/
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void GIC_EnableIRQ(IRQn_Type IRQn);
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/** \brief Disable Interrupt
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Clear-enable bit for each interrupt supported by the GIC.
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\param [in] IRQn Number of the external interrupt to disable
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*/
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void GIC_DisableIRQ(IRQn_Type IRQn);
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/** \brief Set Pending Interrupt
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Set-pending bit for each interrupt supported by the GIC.
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\param [in] IRQn Interrupt number.
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*/
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void GIC_SetPendingIRQ(IRQn_Type IRQn);
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/** \brief Clear Pending Interrupt
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Clear-pending bit for each interrupt supported by the GIC
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\param [in] IRQn Number of the interrupt for clear pending
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*/
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void GIC_ClearPendingIRQ(IRQn_Type IRQn);
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/** \brief Int_config field for each interrupt supported by the GIC.
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This field identifies whether the corresponding interrupt is:
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(1) edge-triggered or (0) level-sensitive
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(1) 1-N model or (0) N-N model
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\param [in] IRQn Interrupt number.
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\param [in] edge_level (1) edge-triggered or (0) level-sensitive
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\param [in] model (1) 1-N model or (0) N-N model
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*/
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void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model);
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/** \brief Set Interrupt Priority
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The function sets the priority of an interrupt.
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\param [in] IRQn Interrupt number.
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\param [in] priority Priority to set.
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*/
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void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority);
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/** \brief Get Interrupt Priority
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The function reads the priority of an interrupt.
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\param [in] IRQn Interrupt number.
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\return Interrupt Priority.
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*/
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uint32_t GIC_GetPriority(IRQn_Type IRQn);
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/** \brief CPU Interface Priority Mask Register
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The priority mask level for the CPU interface. If the priority of an interrupt is higher than the
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value indicated by this field, the interface signals the interrupt to the processor.
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\param [in] Mask.
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*/
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void GIC_InterfacePriorityMask(uint32_t priority);
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/** \brief Set the binary point.
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Set the point at which the priority value fields split into two parts, the group priority field and the subpriority field.
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\param [in] Mask.
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*/
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void GIC_SetBinaryPoint(uint32_t binary_point);
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/** \brief Get the binary point.
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Get the point at which the priority value fields split into two parts, the group priority field and the subpriority field.
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\return Binary point.
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*/
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uint32_t GIC_GetBinaryPoint(uint32_t binary_point);
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/** \brief Get Interrupt state.
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Get the interrupt state, whether pending and/or active
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\return 0 - inactive, 1 - pending, 2 - active, 3 - pending and active
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*/
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uint32_t GIC_GetIRQStatus(IRQn_Type IRQn);
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/** \brief Send Software Generated interrupt
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Provides an interrupt priority filter. Only interrupts with higher priority than the value in this register can be signalled to the processor.
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GIC_InterfacePriorityMask
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\param [in] IRQn The Interrupt ID of the SGI.
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\param [in] target_list CPUTargetList
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\param [in] filter_list TargetListFilter
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*/
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void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list);
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/** \brief API call to initialise the interrupt distributor
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API call to initialise the interrupt distributor
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*/
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void GIC_DistInit(void);
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/** \brief API call to initialise the CPU interface
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API call to initialise the CPU interface
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*/
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void GIC_CPUInterfaceInit(void);
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/** \brief API call to set the Interrupt Configuration Registers
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API call to initialise the Interrupt Configuration Registers
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*/
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void GIC_SetICDICFR (const uint32_t *ICDICFRn);
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/** \brief API call to Enable the GIC
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API call to Enable the GIC
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*/
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void GIC_Enable(void);
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#endif /* GIC_H_ */
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