mirror of https://github.com/ARMmbed/mbed-os.git
480 lines
17 KiB
C
480 lines
17 KiB
C
/****************************************************************************
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*
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* Copyright 2020 Samsung Electronics All Rights Reserved.
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing,
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* software distributed under the License is distributed on an
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* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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* either express or implied. See the License for the specific
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* language governing permissions and limitations under the License.
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*
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****************************************************************************/
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#include "cmsis.h"
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unsigned int cal_clk_is_enabled(unsigned int id)
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{
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return 0;
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}
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int cal_clk_setrate(unsigned int id, unsigned long rate)
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{
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unsigned long parents;
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unsigned int div;
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unsigned int sel;
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switch (id) {
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case p1_upll:
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if (rate == 0) {
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modifyreg32(SCMU_PLL_CON0_UPLL, (1 << 4), 0 << 4);
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modifyreg32(SCMU_PLL_CON0_UPLL, (0x1 << 31), 0);
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} else if ((getreg32(SCMU_PLL_CON0_UPLL) & (1 << 31)) == 0) {
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modifyreg32(SCMU_PLL_CON0_UPLL, (0x1 << 31), 1);
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while (!(getreg32(SCMU_PLL_CON0_UPLL) & (1 << 29))) {
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};
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modifyreg32(SCMU_PLL_CON0_UPLL, (1 << 4), 1 << 4);
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}
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break;
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case m1_timer1:
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if ((rate >= OSCCLK) || (rate == 0)) {
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sel = 0;
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} else {
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sel = 1;
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}
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modifyreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER1_CLK, 1, sel);
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break;
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case m1_timer2:
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if ((rate >= OSCCLK) || (rate == 0)) {
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sel = 0;
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} else {
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sel = 1;
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}
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modifyreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER2_CLK, 1, sel);
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break;
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case m1_timer3:
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if ((rate >= OSCCLK) || (rate == 0)) {
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sel = 0;
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} else {
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sel = 1;
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}
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modifyreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER3_CLK, 1, sel);
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break;
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case m1_timer4:
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if ((rate >= OSCCLK) || (rate == 0)) {
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sel = 0;
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} else {
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sel = 1;
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}
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modifyreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER4_CLK, 1, sel);
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break;
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case m1_timer5:
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if ((rate >= OSCCLK) || (rate == 0)) {
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sel = 0;
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} else {
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sel = 1;
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}
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modifyreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER5_CLK, 1, sel);
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break;
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case d1_upll_clk_ap:
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parents = cal_clk_getrate(p1_upll);
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div = (parents + rate - 1) / rate;
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if (div > 0xf) {
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div = 0xf;
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}
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modifyreg32(SCMU_CLK_CON_DIV_CKDIVS_UPLL_CLK_AP, 0xF, div - 1);
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break;
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case d1_upll_clk_cp:
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parents = cal_clk_getrate(p1_upll);
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div = (parents + rate - 1) / rate;
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if (div > 0xf) {
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div = 0xf;
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}
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modifyreg32(SCMU_CLK_CON_DIV_CKDIVS_UPLL_CLK_CP, 0xF, div - 1);
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break;
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case d1_upll_clk_mif:
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parents = cal_clk_getrate(p1_upll);
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div = (parents + rate - 1) / rate;
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if (div > 0xf) {
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div = 0xf;
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}
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modifyreg32(SCMU_CLK_CON_DIV_CKDIVS_UPLL_CLK_MIF, 0xF, div - 1);
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break;
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case d1_upll_clk_gnss:
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parents = cal_clk_getrate(p1_upll);
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div = (parents + rate - 1) / rate;
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if (div > 0xf) {
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div = 0xf;
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}
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modifyreg32(SCMU_CLK_CON_DIV_CKDIVS_UPLL_CLK_GNSS, 0xF, div - 1);
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break;
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case d1_acpu_l1:
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parents = cal_clk_getrate(d1_upll_clk_ap);
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div = (parents + rate - 1) / rate;
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if (div > 0x1f) {
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div = 0x1f;
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}
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modifyreg32(ACMU_CLK_CON_DIV_MULTI3_CKDIVA_ACPU_CLK, 0x1F, div - 1);
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break;
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case d1_acpu_l2:
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parents = cal_clk_getrate(d1_upll_clk_ap);
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div = (parents + rate - 1) / rate;
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if (div > 0x1f) {
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div = 0x1f;
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}
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modifyreg32(ACMU_CLK_CON_DIV_MULTI3_CKDIVA_ACPU_CLK, 0x1F << 8, (div - 1) << 8);
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break;
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case d1_acpu_l3:
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parents = cal_clk_getrate(d1_upll_clk_ap);
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div = (parents + rate - 1) / rate;
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if (div > 0x1f) {
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div = 0x1f;
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}
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modifyreg32(ACMU_CLK_CON_DIV_MULTI3_CKDIVA_ACPU_CLK, 0x1F << 16, (div - 1) << 16);
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break;
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case d1_sdio:
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parents = cal_clk_getrate(d1_upll_clk_ap);
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div = (parents + rate - 1) / rate;
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if (div > 0x7f) {
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div = 0x7f;
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}
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modifyreg32(ACMU_CLK_CON_DIV_CKDIVA_SDIO_CLK, 0x7F, div - 1);
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break;
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case d1_spi0:
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parents = cal_clk_getrate(d1_upll_clk_ap);
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div = (parents + rate - 1) / rate;
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if (div > 0x1F) {
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div = 0x1F;
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}
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modifyreg32(ACMU_CLK_CON_DIV_CKDIVA_SPI0_CLK, 0x1F, div - 1);
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break;
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case d1_usi0:
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parents = cal_clk_getrate(d1_upll_clk_ap);
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div = (parents + rate - 1) / rate;
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if (div > 0x1F) {
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div = 0x1F;
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}
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modifyreg32(ACMU_CLK_CON_DIV_CKDIVA_USI0_CLK, 0x1F, div - 1);
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break;
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case d1_usi1:
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parents = cal_clk_getrate(d1_upll_clk_ap);
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div = (parents + rate - 1) / rate;
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if (div > 0x1F) {
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div = 0x1F;
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}
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modifyreg32(ACMU_CLK_CON_DIV_CKDIVA_USI1_CLK, 0x1F, div - 1);
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break;
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case d1_mif_l2:
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parents = cal_clk_getrate(d1_upll_clk_mif);
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div = (parents + rate - 1) / rate;
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if (div > 0x1f) {
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div = 0x1f;
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}
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modifyreg32(MIFCMU_CLK_CON_DIV_MULTI2_CKDIVF_MIF_SRC_CLK, 0x1F << 0, (div - 1) << 0);
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break;
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case d1_mif_l3:
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parents = cal_clk_getrate(d1_upll_clk_mif);
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div = (parents + rate - 1) / rate;
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if (div > 0x1f) {
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div = 0x1f;
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}
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modifyreg32(MIFCMU_CLK_CON_DIV_MULTI2_CKDIVF_MIF_SRC_CLK, 0x1F << 8, (div - 1) << 8);
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break;
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case d1_qspi:
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parents = cal_clk_getrate(d1_upll_clk_mif);
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div = (parents + rate - 1) / rate;
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if (div > 0x1F) {
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div = 0x1F;
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}
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modifyreg32(MIFCMU_CLK_CON_DIV_CKDIVF_QSPI_CLK, 0x1F, div - 1);
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break;
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case d1_smc:
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parents = cal_clk_getrate(d1_upll_clk_mif);
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div = (parents + rate - 1) / rate;
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if (div > 0x1F) {
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div = 0x1F;
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}
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modifyreg32(MIFCMU_CLK_CON_DIV_CKDIVF_SMC_CLK, 0x1F, div - 1);
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break;
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case d1_uart0:
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parents = cal_clk_getrate(d1_upll_clk_mif);
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div = (parents + rate - 1) / rate;
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if (div > 0x1F) {
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div = 0x1F;
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}
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modifyreg32(MIFCMU_CLK_CON_DIV_CKDIVF_UART0_CLK, 0x1F, div - 1);
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break;
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case d1_uart1:
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parents = cal_clk_getrate(d1_upll_clk_mif);
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div = (parents + rate - 1) / rate;
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if (div > 0x1F) {
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div = 0x1F;
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}
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modifyreg32(MIFCMU_CLK_CON_DIV_CKDIVF_UART1_CLK, 0x1F, div - 1);
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break;
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default:
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break;
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}
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return 0;
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}
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unsigned long cal_clk_getrate(unsigned int id)
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{
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unsigned long parents;
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unsigned long rate = 0;
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unsigned long div;
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switch (id) {
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case p1_upll:
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if (((getreg32(SCMU_PLL_CON0_UPLL) >> 4) & 1) == 0) {
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rate = OSCCLK;
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} else {
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unsigned long p, m, s;
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p = (getreg32(SCMU_PLL_CON0_UPLL) >> 8) & 0x3f;
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m = (getreg32(SCMU_PLL_CON0_UPLL) >> 16) & 0x3ff;
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s = (getreg32(SCMU_PLL_CON0_UPLL) >> 0) & 0x7;
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rate = (OSCCLK / p * m) >> s;
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}
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break;
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case m1_timer0:
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if ((getreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER0_CLK) & 1) == 0) {
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rate = OSCCLK;
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} else {
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rate = SLPCLK_CP;
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}
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break;
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case m1_timer1:
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if ((getreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER1_CLK) & 1) == 0) {
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rate = OSCCLK;
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} else {
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rate = SLPCLK_CP;
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}
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break;
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case m1_timer2:
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if ((getreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER2_CLK) & 1) == 0) {
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rate = OSCCLK;
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} else {
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rate = SLPCLK_CP;
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}
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break;
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case m1_timer3:
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if ((getreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER3_CLK) & 1) == 0) {
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rate = OSCCLK;
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} else {
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rate = SLPCLK_CP;
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}
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break;
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case m1_timer4:
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if ((getreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER4_CLK) & 1) == 0) {
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rate = OSCCLK;
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} else {
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rate = SLPCLK_CP;
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}
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break;
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case m1_timer5:
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if ((getreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER5_CLK) & 1) == 0) {
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rate = OSCCLK;
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} else {
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rate = SLPCLK_CP;
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}
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break;
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case d1_upll_clk_ap:
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parents = cal_clk_getrate(p1_upll);
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div = (getreg32(SCMU_CLK_CON_DIV_CKDIVS_UPLL_CLK_AP) & 0xF) + 1;
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rate = parents / div;
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break;
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case d1_upll_clk_cp:
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parents = cal_clk_getrate(p1_upll);
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div = (getreg32(SCMU_CLK_CON_DIV_CKDIVS_UPLL_CLK_CP) & 0xF) + 1;
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rate = parents / div;
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break;
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case d1_upll_clk_mif:
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parents = cal_clk_getrate(p1_upll);
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div = (getreg32(SCMU_CLK_CON_DIV_CKDIVS_UPLL_CLK_MIF) & 0xF) + 1;
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rate = parents / div;
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break;
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case d1_upll_clk_gnss:
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parents = cal_clk_getrate(p1_upll);
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div = (getreg32(SCMU_CLK_CON_DIV_CKDIVS_UPLL_CLK_GNSS) & 0xF) + 1;
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rate = parents / div;
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break;
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case d1_acpu_l1:
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parents = cal_clk_getrate(d1_upll_clk_ap);
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div = (getreg32(ACMU_CLK_CON_DIV_MULTI3_CKDIVA_ACPU_CLK) & 0x1F) + 1;
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rate = parents / div;
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break;
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case d1_acpu_l2:
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parents = cal_clk_getrate(d1_upll_clk_ap);
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div = ((getreg32(ACMU_CLK_CON_DIV_MULTI3_CKDIVA_ACPU_CLK) >> 8) & 0x1F) + 1;
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rate = parents / div;
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break;
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case d1_acpu_l3:
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parents = cal_clk_getrate(d1_upll_clk_ap);
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div = ((getreg32(ACMU_CLK_CON_DIV_MULTI3_CKDIVA_ACPU_CLK) >> 16) & 0x1F) + 1;
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rate = parents / div;
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break;
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case d1_sdio:
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parents = cal_clk_getrate(d1_upll_clk_ap);
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div = (getreg32(ACMU_CLK_CON_DIV_CKDIVA_SDIO_CLK) & 0x7F) + 1;
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rate = parents / div;
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break;
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case d1_spi0:
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parents = cal_clk_getrate(d1_upll_clk_ap);
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div = (getreg32(ACMU_CLK_CON_DIV_CKDIVA_SPI0_CLK) & 0x1F) + 1;
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rate = parents / div;
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break;
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case d1_usi0:
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parents = cal_clk_getrate(d1_upll_clk_ap);
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div = (getreg32(ACMU_CLK_CON_DIV_CKDIVA_USI0_CLK) & 0x1F) + 1;
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rate = parents / div;
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break;
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case d1_usi1:
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parents = cal_clk_getrate(d1_upll_clk_ap);
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div = (getreg32(ACMU_CLK_CON_DIV_CKDIVA_USI1_CLK) & 0x1F) + 1;
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rate = parents / div;
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break;
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case d1_mif_l2:
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parents = cal_clk_getrate(d1_upll_clk_mif);
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div = ((getreg32(MIFCMU_CLK_CON_DIV_MULTI2_CKDIVF_MIF_SRC_CLK) >> 0) & 0x1F) + 1;
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rate = parents / div;
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break;
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case d1_mif_l3:
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parents = cal_clk_getrate(d1_upll_clk_mif);
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div = ((getreg32(MIFCMU_CLK_CON_DIV_MULTI2_CKDIVF_MIF_SRC_CLK) >> 8) & 0x1F) + 1;
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rate = parents / div;
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break;
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case d1_qspi:
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parents = cal_clk_getrate(d1_upll_clk_mif);
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div = (getreg32(MIFCMU_CLK_CON_DIV_CKDIVF_QSPI_CLK) & 0x1F) + 1;
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rate = parents / div;
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break;
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case d1_smc:
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parents = cal_clk_getrate(d1_upll_clk_mif);
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div = (getreg32(MIFCMU_CLK_CON_DIV_CKDIVF_SMC_CLK) & 0x1F) + 1;
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rate = parents / div;
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break;
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case d1_uart0:
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parents = cal_clk_getrate(d1_upll_clk_mif);
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div = (getreg32(MIFCMU_CLK_CON_DIV_CKDIVF_UART0_CLK) & 0x1F) + 1;
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rate = parents / div;
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break;
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case d1_uart1:
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parents = cal_clk_getrate(d1_upll_clk_mif);
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div = (getreg32(MIFCMU_CLK_CON_DIV_CKDIVF_UART1_CLK) & 0x1F) + 1;
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rate = parents / div;
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break;
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default:
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break;
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}
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return rate;
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}
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int cal_clk_enable(unsigned int id)
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{
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switch (id) {
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case p1_upll:
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modifyreg32(SCMU_PLL_CON0_UPLL, (0x1 << 31), 1);
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while (!(getreg32(SCMU_PLL_CON0_UPLL) & (1 << 29))) {
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};
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modifyreg32(SCMU_PLL_CON0_UPLL, (1 << 4), 1 << 4);
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break;
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default:
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break;
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}
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return 0;
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}
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int cal_clk_disable(unsigned int id)
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{
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switch (id) {
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case p1_upll:
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modifyreg32(SCMU_PLL_CON0_UPLL, (1 << 4), 0 << 4);
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modifyreg32(SCMU_PLL_CON0_UPLL, (0x1 << 31), 0);
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break;
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default:
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break;
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}
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return 0;
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}
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int cal_init(void)
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{
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/* disable 0 value setting to reduce binary size */
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/* enable UPLL */
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modifyreg32(SCMU_PLL_CON0_UPLL, (0x3ff << 16), (0x18c << 16));
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modifyreg32(SCMU_PLL_CON0_UPLL, (0x1 << 31), (1 << 31));
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modifyreg32(SCMU_CLK_CON_DIV_CKDIVS_UPLL_CLK_AP, 0xf, 1);
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/* need to fix to 0x1 */
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modifyreg32(SCMU_CLK_CON_DIV_CKDIVS_UPLL_CLK_MIF, 0xf, 0x1);
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// modifyreg32(ACMU_CLK_CON_DIV_MULTI3_CKDIVA_ACPU_CLK, (0x1f << 0), 0); /* L1 CLK */
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// modifyreg32(ACMU_CLK_CON_DIV_MULTI3_CKDIVA_ACPU_CLK, (0x1f << 8), 0); /* L2 CLK */
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modifyreg32(ACMU_CLK_CON_DIV_MULTI3_CKDIVA_ACPU_CLK, (0x1f << 16), 1 << 16); /* L3 CLK */
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// modifyreg32(ACMU_CLK_CON_DIV_CKDIVA_SDIO_CLK, 0x7f, 0);
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modifyreg32(ACMU_CLK_CON_DIV_CKDIVA_SPI0_CLK, 0x1f, 1);
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// modifyreg32(ACMU_CLK_CON_DIV_CKDIVA_USI0_CLK, 0x1f, 0);
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// modifyreg32(ACMU_CLK_CON_DIV_CKDIVA_USI1_CLK, 0x1f, 0);
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// modifyreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER0_CLK, 0x1, 0);
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// modifyreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER1_CLK, 0x1, 0);
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// modifyreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER2_CLK, 0x1, 0);
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// modifyreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER3_CLK, 0x1, 0);
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// modifyreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER4_CLK, 0x1, 0);
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// modifyreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER5_CLK, 0x1, 0);
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// modifyreg32(MIFCMU_CLK_CON_DIV_MULTI2_CKDIVF_MIF_SRC_CLK, (0x1f << 0), 0); /* L2 CLK */
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modifyreg32(MIFCMU_CLK_CON_DIV_MULTI2_CKDIVF_MIF_SRC_CLK, (0x1f << 8), 1 << 8); /* L3 CLK */
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modifyreg32(MIFCMU_CLK_CON_DIV_CKDIVF_QSPI_CLK, 0x1f, 4); //QSPI_CLK to be 40Mhz as first
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modifyreg32(MIFCMU_CLK_CON_DIV_CKDIVF_SMC_CLK, 0x1f, 1);
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modifyreg32(MIFCMU_CLK_CON_DIV_CKDIVF_UART0_CLK, 0x1f, 1);
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modifyreg32(MIFCMU_CLK_CON_DIV_CKDIVF_UART1_CLK, 0x1f, 1);
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/* wait for UPLL lock */
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while (!(getreg32(SCMU_PLL_CON0_UPLL) & (1 << 29))) {
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};
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modifyreg32(SCMU_PLL_CON0_UPLL, (0x1 << 4), (1 << 4));
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#if 0
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/* Q-CHANNEL enable */
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//modifyreg32(ACMU_AP_ACMU_CONTROLLER_OPTION, (0x3 << 28), (0x3 << 28));
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modifyreg32(SCMU_SYS_SCMU_CONTROLLER_OPTION, (0x3 << 28), (0x3 << 28));
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modifyreg32(MIFCMU_MIF_MIFCMU_CONTROLLER_OPTION, (0x3 << 28), (0x3 << 28));
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/* BUS_FREQ_EN, MIN_FREQ_EN enable */
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modifyreg32(ACMU_ACMU_DFSC_CTL, (0x3 << 1), (0x3 << 1));
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#endif
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/* PDMAC Q-CH workaround */
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putreg32(0x4046, ACMU_ACMU_BUS_ACT_MSK);
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/* Gate clocks of unused peripherals */
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// SDIO HOST
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putreg32(0x100000, ACMU_CLK_CON_GAT_GOUT_AP_UID_SDIO_IPCLKPORT_CLK);
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putreg32(0x100000, ACMU_CLK_CON_GAT_GOUT_AP_UID_SDIO_IPCLKPORT_L2CLK);
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putreg32(0x100000, ACMU_CLK_CON_GAT_GOUT_AP_UID_SDIO_IPCLKPORT_SDIO_HCLK);
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// PPMUs
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putreg32(0x100000, ACMU_CLK_CON_GAT_GOUT_AP_UID_ABUS_IPCLKPORT_PPMU_L2CLK);
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putreg32(0x100000, ACMU_CLK_CON_GAT_GOUT_AP_UID_ABUS_IPCLKPORT_PPMU_L3CLK);
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putreg32(0x100000, MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_MIFBUS_IPCLKPORT_PPMU_ACPU2MIF_L2CLK);
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putreg32(0x100000, MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_MIFBUS_IPCLKPORT_PPMU_ACPU2MIF_L3CLK);
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putreg32(0x100000, MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_MIFBUS_IPCLKPORT_PPMU_MCPU2MIF_L2CLK);
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putreg32(0x100000, MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_MIFBUS_IPCLKPORT_PPMU_MCPU2MIF_L3CLK);
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// SMC
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putreg32(0x100000, MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_SMC_IPCLKPORT_CLK);
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putreg32(0x100000, MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_SMC_IPCLKPORT_L2CLK);
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return 0;
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}
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