mirror of https://github.com/ARMmbed/mbed-os.git
155 lines
6.0 KiB
C
155 lines
6.0 KiB
C
/*******************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only
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* intended for use with Renesas products. No other uses are authorized. This
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* software is owned by Renesas Electronics Corporation and is protected under
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* all applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software
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* and to discontinue the availability of this software. By using this software,
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* you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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*
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* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
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*******************************************************************************/
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/******************************************************************************
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* File Name : spibsc.h
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* $Rev: 12 $
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* $Date:: 2016-05-19 17:26:37 +0900#$
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* Description :
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******************************************************************************/
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#ifndef _SPIBSC_H_
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#define _SPIBSC_H_
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/******************************************************************************
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Includes <System Includes> , "Project Includes"
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******************************************************************************/
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#include "iodefine.h"
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/******************************************************************************
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Macro definitions
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******************************************************************************/
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#define SPIBSC_CMNCR_MD_EXTRD (0u)
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#define SPIBSC_CMNCR_MD_SPI (1u)
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#define SPIBSC_OUTPUT_LOW (0u)
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#define SPIBSC_OUTPUT_HIGH (1u)
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#define SPIBSC_OUTPUT_LAST (2u)
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#define SPIBSC_OUTPUT_HiZ (3u)
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#define SPIBSC_CMNCR_CPHAT_EVEN (0u)
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#define SPIBSC_CMNCR_CPHAT_ODD (1u)
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#define SPIBSC_CMNCR_CPHAR_ODD (0u)
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#define SPIBSC_CMNCR_CPHAR_EVEN (1u)
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#define SPIBSC_CMNCR_SSLP_LOW (0u)
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#define SPIBSC_CMNCR_SSLP_HIGH (1u)
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#define SPIBSC_CMNCR_CPOL_LOW (0u)
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#define SPIBSC_CMNCR_CPOL_HIGH (1u)
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#define SPIBSC_CMNCR_BSZ_SINGLE (0u)
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#define SPIBSC_CMNCR_BSZ_DUAL (1u)
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#define SPIBSC_DELAY_1SPBCLK (0u)
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#define SPIBSC_DELAY_2SPBCLK (1u)
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#define SPIBSC_DELAY_3SPBCLK (2u)
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#define SPIBSC_DELAY_4SPBCLK (3u)
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#define SPIBSC_DELAY_5SPBCLK (4u)
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#define SPIBSC_DELAY_6SPBCLK (5u)
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#define SPIBSC_DELAY_7SPBCLK (6u)
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#define SPIBSC_DELAY_8SPBCLK (7u)
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#define SPIBSC_BURST_1 (0x00u)
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#define SPIBSC_BURST_2 (0x01u)
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#define SPIBSC_BURST_3 (0x02u)
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#define SPIBSC_BURST_4 (0x03u)
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#define SPIBSC_BURST_5 (0x04u)
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#define SPIBSC_BURST_6 (0x05u)
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#define SPIBSC_BURST_7 (0x06u)
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#define SPIBSC_BURST_8 (0x07u)
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#define SPIBSC_BURST_9 (0x08u)
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#define SPIBSC_BURST_10 (0x09u)
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#define SPIBSC_BURST_11 (0x0au)
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#define SPIBSC_BURST_12 (0x0bu)
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#define SPIBSC_BURST_13 (0x0cu)
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#define SPIBSC_BURST_14 (0x0du)
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#define SPIBSC_BURST_15 (0x0eu)
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#define SPIBSC_BURST_16 (0x0fu)
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#define SPIBSC_BURST_DISABLE (0u)
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#define SPIBSC_BURST_ENABLE (1u)
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#define SPIBSC_DRCR_RCF_EXE (1u)
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#define SPIBSC_SSL_NEGATE (0u)
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#define SPIBSC_TRANS_END (1u)
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#define SPIBSC_1BIT (0u)
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#define SPIBSC_2BIT (1u)
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#define SPIBSC_4BIT (2u)
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#define SPIBSC_OUTPUT_DISABLE (0u)
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#define SPIBSC_OUTPUT_ENABLE (1u)
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#define SPIBSC_OUTPUT_ADDR_24 (0x07u)
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#define SPIBSC_OUTPUT_ADDR_32 (0x0fu)
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#define SPIBSC_OUTPUT_OPD_3 (0x08u)
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#define SPIBSC_OUTPUT_OPD_32 (0x0cu)
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#define SPIBSC_OUTPUT_OPD_321 (0x0eu)
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#define SPIBSC_OUTPUT_OPD_3210 (0x0fu)
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#define SPIBSC_OUTPUT_SPID_8 (0x08u)
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#define SPIBSC_OUTPUT_SPID_16 (0x0cu)
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#define SPIBSC_OUTPUT_SPID_32 (0x0fu)
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#define SPIBSC_SPISSL_NEGATE (0u)
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#define SPIBSC_SPISSL_KEEP (1u)
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#define SPIBSC_SPIDATA_DISABLE (0u)
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#define SPIBSC_SPIDATA_ENABLE (1u)
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#define SPIBSC_SPI_DISABLE (0u)
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#define SPIBSC_SPI_ENABLE (1u)
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/* Use for setting of the DME bit of "data read enable register"(DRENR) */
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#define SPIBSC_DUMMY_CYC_DISABLE (0u)
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#define SPIBSC_DUMMY_CYC_ENABLE (1u)
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/* Use for setting of the DMCYC [2:0] bit of "data read dummy cycle register"(DRDMCR) */
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#define SPIBSC_DUMMY_1CYC (0u)
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#define SPIBSC_DUMMY_2CYC (1u)
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#define SPIBSC_DUMMY_3CYC (2u)
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#define SPIBSC_DUMMY_4CYC (3u)
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#define SPIBSC_DUMMY_5CYC (4u)
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#define SPIBSC_DUMMY_6CYC (5u)
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#define SPIBSC_DUMMY_7CYC (6u)
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#define SPIBSC_DUMMY_8CYC (7u)
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/* Use for setting of "data read DDR enable register"(DRDRENR) */
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#define SPIBSC_SDR_TRANS (0u)
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#define SPIBSC_DDR_TRANS (1u)
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/* Use for setting the CKDLY regsiter */
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#define SPIBSC_CKDLY_DEFAULT (0x0000A504uL) /* Initial value */
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#define SPIBSC_CKDLY_TUNING (0x0000A50AuL) /* Shorten the data input setup time and extend the data hold time */
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/* Use for setting the SPODLY regsiter */
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#define SPIBSC_SPODLY_DEFAULT (0xA5000000uL) /* Initial value */
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#define SPIBSC_SPODLY_TUNING (0xA5001111uL) /* Delay the data output delay/hold/buffer-on/buffer-off time */
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#endif /* _SPIBSC_H_ */
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/* End of File */
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