mirror of https://github.com/ARMmbed/mbed-os.git
337 lines
9.8 KiB
C
337 lines
9.8 KiB
C
/*
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* Copyright (c) 2018 ARM Limited. All rights reserved.
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* SPDX-License-Identifier: Apache-2.0
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef S2LPREG_H_
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#define S2LPREG_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define RF_MTU 2047
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#define PARTNUM 0x03
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#define VERSION 0xC1
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#define FIFO_SIZE 128
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#define SPI_HEADER_LENGTH 2
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#define S2LP_GPIO0 0
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#define S2LP_GPIO1 1
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#define S2LP_GPIO2 2
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#define S2LP_GPIO3 3
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// GPIO modes
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#define DIG_IN 1
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#define DIG_OUT_LOW 2
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#define DIG_OUT_HIGH 3
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// Interrupt events
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#define RX_DATA_READY 0
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#define RX_DATA_DISCARDED 1
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#define TX_DATA_SENT 2
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#define MAX_RE_TX 3
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#define CRC_ERROR 4
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#define TX_FIFO_UNF_OVF 5
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#define RX_FIFO_UNF_OVF 6
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#define TX_FIFO_ALMOST_FULL 7
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#define TX_FIFO_ALMOST_EMPTY 8
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#define RX_FIFO_ALMOST_FULL 9
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#define RX_FIFO_ALMOST_EMPTY 10
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#define MAX_CCA_BACKOFFS 11
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#define VALID_PREAMBLE 12
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#define SYNC_WORD 13
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#define RSSI_ABOVE_THR 14
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#define WAKE_UP_TIMEOUT 15
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#define READY 16
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#define STANDBY_SWITCHING 17
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#define LOW_BATTERY_LVL 18
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#define POWER_ON_RESET 19
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#define RX_TIMER_TIMEOUT 28
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#define SNIFF_TIMER_TIMEOUT 29
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// GPIO signals
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#define NIRQ 0
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#define POR 1
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#define WUT_EXPIRE 2
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#define LOW_BATTERY 3
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#define TX_DATA_OUTPUT 4
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#define TX_STATE 5
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#define TXRX_FIFO_ALMOST_EMPTY 6
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#define TXRX_FIFO_ALMOST_FULL 7
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#define RX_DATA_OUTPUT 8
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#define RX_CLOCK_OUTPUT 9
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#define RX_STATE 10
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#define STATE_OTHER_THAN_SLEEP_OR_STANDBY 11
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#define STANDBY_STATE 12
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#define ANTENNA_SWITCH 13
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#define VALID_PREAMBLE_DETECTED 14
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#define SYNC_WORD_DETECTED 15
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#define RSSI_ABOVE_THRESHOLD 16
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#define TXRX_MODE_INDICATOR 18
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#define VDD 19
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#define GND 20
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#define SMPS_ENABLE 21
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#define SLEEP_STATE 22
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#define READY_STATE 23
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#define LOCK_STATE 24
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#define WAIT_LOCK_DETECTOR 25
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#define TX_DATA_OOK 26
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#define WAIT_READY 27
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#define WAIT_TIMER_EXPIRATION 28
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#define END_OF_CALIBRATION 29
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#define ENABLE_SYNTH_BLOCK 30
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// RF registers
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#define GPIO0_CONF 0x00
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#define GPIO1_CONF 0x01
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#define GPIO2_CONF 0x02
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#define GPIO3_CONF 0x03
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#define SYNT3 0x05
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#define SYNT2 0x06
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#define SYNT1 0x07
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#define SYNT0 0x08
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#define IF_OFFSET_ANA 0x09
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#define IF_OFFSET_DIG 0x0A
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#define CHSPACE 0x0C
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#define CHNUM 0x0D
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#define MOD4 0x0E
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#define MOD3 0x0F
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#define MOD2 0x10
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#define MOD1 0x11
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#define MOD0 0x12
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#define CHFLT 0x13
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#define AFC2 0x14
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#define AFC1 0x15
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#define AFC0 0x16
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#define RSSI_FLT 0x17
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#define RSSI_TH 0x18
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#define AGCCTRL4 0x1A
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#define AGCCTRL3 0x1B
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#define AGCCTRL2 0x1C
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#define AGCCTRL1 0x1D
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#define AGCCTRL0 0x1E
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#define ANT_SELECT_CONF 0x1F
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#define CLOCKREC2 0x20
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#define CLOCKREC1 0x21
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#define PCKTCTRL6 0x2B
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#define PCKTCTRL5 0x2C
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#define PCKTCTRL4 0x2D
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#define PCKTCTRL3 0x2E
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#define PCKTCTRL2 0x2F
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#define PCKTCTRL1 0x30
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#define PCKTLEN1 0x31
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#define PCKTLEN0 0x32
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#define SYNC3 0x33
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#define SYNC2 0x34
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#define SYNC1 0x35
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#define SYNC0 0x36
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#define QI 0x37
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#define PCKT_PSTMBL 0x38
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#define PROTOCOL2 0x39
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#define PROTOCOL1 0x3A
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#define PROTOCOL0 0x3B
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#define FIFO_CONFIG3 0x3C
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#define FIFO_CONFIG2 0x3D
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#define FIFO_CONFIG1 0x3E
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#define FIFO_CONFIG0 0x3F
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#define PCKT_FLT_OPTIONS 0x40
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#define PCKT_FLT_GOALS4 0x41
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#define PCKT_FLT_GOALS3 0x42
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#define PCKT_FLT_GOALS2 0x43
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#define PCKT_FLT_GOALS1 0x44
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#define PCKT_FLT_GOALS0 0x45
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#define TIMERS5 0x46
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#define TIMERS4 0x47
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#define TIMERS3 0x48
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#define TIMERS2 0x49
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#define TIMERS1 0x4A
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#define TIMERS0 0x4B
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#define CSMA_CONF3 0x4C
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#define CSMA_CONF2 0x4D
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#define CSMA_CONF1 0x4E
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#define CSMA_CONF0 0x4F
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#define IRQ_MASK3 0x50
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#define IRQ_MASK2 0x51
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#define IRQ_MASK1 0x52
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#define IRQ_MASK0 0x53
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#define FAST_RX_TIMER 0x54
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#define PA_POWER8 0x5A
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#define PA_POWER7 0x5B
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#define PA_POWER6 0x5C
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#define PA_POWER5 0x5D
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#define PA_POWER4 0x5E
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#define PA_POWER3 0x5F
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#define PA_POWER2 0x60
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#define PA_POWER1 0x61
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#define PA_POWER0 0x62
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#define PA_CONFIG1 0x63
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#define PA_CONFIG0 0x64
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#define SYNTH_CONFIG2 0x65
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#define VCO_CONFIG 0x68
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#define VCO_CALIBR_IN2 0x69
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#define VCO_CALIBR_IN1 0x6A
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#define VCO_CALIBR_IN0 0x6B
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#define XO_RCO_CONF1 0x6C
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#define XO_RCO_CONF0 0x6D
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#define RCO_CALIBR_CONF3 0x6E
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#define RCO_CALIBR_CONF2 0x6F
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#define PM_CONF4 0x75
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#define PM_CONF3 0x76
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#define PM_CONF2 0x77
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#define PM_CONF1 0x78
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#define PM_CONF0 0x79
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#define MC_STATE1 0x8D
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#define MC_STATE0 0x8E
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#define TX_FIFO_STATUS 0x8F
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#define RX_FIFO_STATUS 0x90
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#define RCO_CALIBR_OUT4 0x94
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#define RCO_CALIBR_OUT3 0x95
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#define VCO_CALIBR_OUT1 0x99
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#define VCO_CALIBR_OUT0 0x9A
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#define TX_PCKT_INFO 0x9C
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#define RX_PCKT_INFO 0x9D
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#define AFC_CORR 0x9E
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#define LINK_QUALIF2 0x9F
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#define LINK_QUALIF1 0xA0
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#define RSSI_LEVEL 0xA2
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#define RX_PCKT_LEN1 0xA4
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#define RX_PCKT_LEN0 0xA5
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#define CRC_FIELD3 0xA6
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#define CRC_FIELD2 0xA7
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#define CRC_FIELD1 0xA8
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#define CRC_FIELD0 0xA9
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#define RX_ADDRE_FIELD1 0xAA
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#define RX_ADDRE_FIELD0 0xAB
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#define RSSI_LEVEL_RUN 0xEF
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#define DEVICE_INFO1 0xF0
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#define DEVICE_INFO0 0xF1
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#define IRQ_STATUS3 0xFA
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#define IRQ_STATUS2 0xFB
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#define IRQ_STATUS1 0xFC
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#define IRQ_STATUS0 0xFD
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#define TX_FIFO 0xFF
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#define RX_FIFO 0xFF
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#define SFD0 0x90
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#define SFD1 0x4e
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#define DEVIATION 125000
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#define RX_FILTER_BANDWIDTH 540000
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#define RSSI_THRESHOLD -60
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// PCKTCTRL6
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#define PCKT_SYNCLEN_FIELD 0xFC
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#define PCKT_SYNCLEN (16 << 2)
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// PCKTCTRL5
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#define PCKT_PREAMBLE_LEN 32
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// PCKTCTRL3
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#define PCKT_FORMAT_FIELD 0xC0
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#define PCKT_FORMAT_802_15_4 (1 << 6)
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#define PCKT_RXMODE_FIELD 0x30
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#define PCKT_RXMODE_NORMAL (0 << 4)
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// PCKTCTRL2
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#define PCKT_FIXVARLEN_FIELD 0x01
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#define PCKT_VARIABLE_LEN (1 << 0)
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// PCKTCTRL1
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#define PCKT_CRCMODE_FIELD 0xE0
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#define PCKT_CRCMODE_0X1021 (3 << 5)
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#define PCKT_TXSOURCE_FIELD 0x0C
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#define PCKT_TXSOURCE_NORMAL (0 << 2)
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#define PCKT_WHITENING_FIELD 0x10
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#define PCKT_WHITENING_ENABLED (1 << 4)
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// MOD4
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#define DATARATE_M_MSB 0x47
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// MOD3
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#define DATARATE_M_LSB 0xAE
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// MOD2
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#define MOD_TYPE_FIELD 0xF0
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#define MOD_2FSK (0 << 4)
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#define MOD_2GFSK (10 << 4)
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#define DATARATE_E_FIELD 0x0F
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#define DATARATE_E (10 << 0)
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// MOD1
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#define FDEV_E_FIELD 0x0F
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// QI
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#define PQI_TH_FIELD 0x1E
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#define PQI_TH (8 << 1)
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#define SQI_EN_FIELD 0x01
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#define SQI_EN (1 << 0)
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// SYNT3
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#define SYNT_FIELD 0x0F
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// CHFLT
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#define CHFLT_M_FIELD 0xF0
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#define CHFLT_E_FIELD 0x0F
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// LINK_QUALIF1
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#define CARRIER_SENSE (1 << 7)
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#define SPI_WR_REG 0x00
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#define SPI_RD_REG 0x01
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#define SPI_CMD 0x80
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typedef enum {
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S2LP_STATE_STANDBY = 0x02,
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S2LP_STATE_SLEEPA = 0x01,
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S2LP_STATE_SLEEPB = 0x03,
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S2LP_STATE_READY = 0x00,
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S2LP_STATE_LOCK = 0x0C,
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S2LP_STATE_RX = 0x30,
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S2LP_STATE_TX = 0x5C,
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S2LP_STATE_SYNTH_SETUP = 0x50
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} s2lp_states_e;
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#if defined __cplusplus && __cplusplus >= 201103
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typedef enum : uint8_t {
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#else
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typedef enum {
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#endif
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S2LP_CMD_TX = 0x60,
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S2LP_CMD_RX,
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S2LP_CMD_READY,
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S2LP_CMD_STANDBY,
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S2LP_CMD_SLEEP,
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S2LP_CMD_LOCKRX,
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S2LP_CMD_LOCKTX,
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S2LP_CMD_SABORT,
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S2LP_CMD_LDC_RELOAD,
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S2LP_CMD_SRES = 0x70,
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S2LP_CMD_FLUSHRXFIFO,
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S2LP_CMD_FLUSHTXFIFO,
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S2LP_CMD_SEQUPDATE
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} s2lp_commands_e;
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typedef enum {
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RF_IDLE,
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RF_CSMA_STARTED,
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RF_TX_STARTED,
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RF_RX_STARTED,
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RF_TX_ACK
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} rf_states_e;
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#ifdef __cplusplus
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}
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#endif
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#endif /* S2LPREG_H_ */
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