mirror of https://github.com/ARMmbed/mbed-os.git
276 lines
6.5 KiB
C
276 lines
6.5 KiB
C
/* mbed Microcontroller Library
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* Copyright (c) 2006-2013 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "mbed_assert.h"
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#include <math.h>
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#include "spi_api.h"
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#include "cmsis.h"
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#include "pinmap.h"
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#include "mbed_error.h"
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static const SWM_Map SWM_SPI_SSEL[] = {
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{4, 16},
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{5, 16},
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};
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static const SWM_Map SWM_SPI_SCLK[] = {
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{3, 24},
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{4, 24},
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};
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static const SWM_Map SWM_SPI_MOSI[] = {
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{4, 0},
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{5, 0},
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};
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static const SWM_Map SWM_SPI_MISO[] = {
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{4, 8},
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{5, 16},
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};
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// Pinmap used for testing only
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static const PinMap PinMap_SPI_testing[] = {
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{P0_0, 0, 0},
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{P0_1, 0, 0},
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{P0_2, 0, 0},
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{P0_3, 0, 0},
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{P0_4, 0, 0},
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{P0_5, 0, 0},
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{P0_6, 0, 0},
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{P0_7, 0, 0},
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{P0_8, 0, 0},
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{P0_9, 0, 0},
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{P0_10, 0, 0},
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{P0_11, 0, 0},
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{P0_12, 0, 0},
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{P0_13, 0, 0},
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{P0_14, 0, 0},
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{P0_15, 0, 0},
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{P0_16, 0, 0},
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{P0_17, 0, 0},
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{NC, NC, 0}
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};
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// bit flags for used SPIs
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static unsigned char spi_used = 0;
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static int get_available_spi(void) {
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int i;
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for (i=0; i<2; i++) {
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if ((spi_used & (1 << i)) == 0)
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return i;
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}
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return -1;
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}
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static inline int ssp_disable(spi_t *obj);
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static inline int ssp_enable(spi_t *obj);
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void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
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int spi_n = get_available_spi();
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if (spi_n == -1) {
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error("No available SPI");
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}
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obj->spi_n = spi_n;
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spi_used |= (1 << spi_n);
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obj->spi = (spi_n) ? (LPC_SPI_TypeDef *)(LPC_SPI1_BASE) : (LPC_SPI_TypeDef *)(LPC_SPI0_BASE);
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const SWM_Map *swm;
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uint32_t regVal;
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swm = &SWM_SPI_SCLK[obj->spi_n];
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regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
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LPC_SWM->PINASSIGN[swm->n] = regVal | (sclk << swm->offset);
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swm = &SWM_SPI_MOSI[obj->spi_n];
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regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
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LPC_SWM->PINASSIGN[swm->n] = regVal | (mosi << swm->offset);
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swm = &SWM_SPI_MISO[obj->spi_n];
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regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
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LPC_SWM->PINASSIGN[swm->n] = regVal | (miso << swm->offset);
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swm = &SWM_SPI_SSEL[obj->spi_n];
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regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
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LPC_SWM->PINASSIGN[swm->n] = regVal | (ssel << swm->offset);
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// clear interrupts
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obj->spi->INTENCLR = 0x3f;
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// enable power and clocking
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switch (obj->spi_n) {
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case 0:
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LPC_SYSCON->SYSAHBCLKCTRL |= (1<<11);
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LPC_SYSCON->PRESETCTRL &= ~(0x1<<0);
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LPC_SYSCON->PRESETCTRL |= (0x1<<0);
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break;
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case 1:
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LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12);
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LPC_SYSCON->PRESETCTRL &= ~(0x1<<1);
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LPC_SYSCON->PRESETCTRL |= (0x1<<1);
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break;
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}
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}
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void spi_free(spi_t *obj) {}
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void spi_format(spi_t *obj, int bits, int mode, int slave) {
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MBED_ASSERT(((bits >= 1) && (bits <= 16)) && ((mode >= 0) && (mode <= 3)));
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ssp_disable(obj);
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int polarity = (mode & 0x2) ? 1 : 0;
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int phase = (mode & 0x1) ? 1 : 0;
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// set it up
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int DSS = bits - 1; // DSS (data select size)
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int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
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int SPH = (phase) ? 1 : 0; // SPH - clock out phase
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uint32_t tmp = obj->spi->CFG;
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tmp &= ~((1 << 2) | (1 << 4) | (1 << 5));
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tmp |= (SPH << 4) | (SPO << 5) | ((slave ? 0 : 1) << 2);
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obj->spi->CFG = tmp;
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// select frame length
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tmp = obj->spi->TXDATCTL;
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tmp &= ~(0xf << 24);
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tmp |= (DSS << 24);
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obj->spi->TXDATCTL = tmp;
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ssp_enable(obj);
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}
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void spi_frequency(spi_t *obj, int hz) {
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ssp_disable(obj);
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uint32_t PCLK = SystemCoreClock;
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obj->spi->DIV = PCLK/hz - 1;
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obj->spi->DLY = 0;
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ssp_enable(obj);
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}
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static inline int ssp_disable(spi_t *obj) {
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return obj->spi->CFG &= ~(1 << 0);
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}
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static inline int ssp_enable(spi_t *obj) {
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return obj->spi->CFG |= (1 << 0);
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}
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static inline int ssp_readable(spi_t *obj) {
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return obj->spi->STAT & (1 << 0);
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}
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static inline int ssp_writeable(spi_t *obj) {
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return obj->spi->STAT & (1 << 1);
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}
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static inline void ssp_write(spi_t *obj, int value) {
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while (!ssp_writeable(obj));
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// end of transfer
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obj->spi->TXDATCTL |= (1 << 20);
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obj->spi->TXDAT = value;
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}
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static inline int ssp_read(spi_t *obj) {
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while (!ssp_readable(obj));
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return obj->spi->RXDAT;
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}
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static inline int ssp_busy(spi_t *obj) {
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// checking RXOV(Receiver Overrun interrupt flag)
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return obj->spi->STAT & (1 << 2);
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}
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int spi_master_write(spi_t *obj, int value) {
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ssp_write(obj, value);
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return ssp_read(obj);
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}
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int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
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char *rx_buffer, int rx_length, char write_fill) {
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int total = (tx_length > rx_length) ? tx_length : rx_length;
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for (int i = 0; i < total; i++) {
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char out = (i < tx_length) ? tx_buffer[i] : write_fill;
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char in = spi_master_write(obj, out);
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if (i < rx_length) {
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rx_buffer[i] = in;
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}
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}
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return total;
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}
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int spi_slave_receive(spi_t *obj) {
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return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
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}
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int spi_slave_read(spi_t *obj) {
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return obj->spi->RXDAT;
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}
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void spi_slave_write(spi_t *obj, int value) {
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while (ssp_writeable(obj) == 0) ;
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obj->spi->TXDAT = value;
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}
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int spi_busy(spi_t *obj) {
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return ssp_busy(obj);
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}
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const PinMap *spi_master_mosi_pinmap()
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{
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return PinMap_SPI_testing;
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}
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const PinMap *spi_master_miso_pinmap()
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{
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return PinMap_SPI_testing;
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}
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const PinMap *spi_master_clk_pinmap()
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{
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return PinMap_SPI_testing;
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}
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const PinMap *spi_master_cs_pinmap()
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{
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return PinMap_SPI_testing;
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}
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const PinMap *spi_slave_mosi_pinmap()
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{
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return PinMap_SPI_testing;
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}
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const PinMap *spi_slave_miso_pinmap()
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{
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return PinMap_SPI_testing;
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}
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const PinMap *spi_slave_clk_pinmap()
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{
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return PinMap_SPI_testing;
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}
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const PinMap *spi_slave_cs_pinmap()
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{
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return PinMap_SPI_testing;
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}
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