mirror of https://github.com/ARMmbed/mbed-os.git
292 lines
12 KiB
C
292 lines
12 KiB
C
/**
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******************************************************************************
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* @file rfAna.c
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* @brief Implementation of rfAna hw module functions
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* @internal
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* @author ON Semiconductor
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* $Rev: 3445 $
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* $Date: 2015-06-22 13:51:24 +0530 (Mon, 22 Jun 2015) $
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******************************************************************************
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* Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
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* All rights reserved. This software and/or documentation is licensed by ON Semiconductor
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* under limited terms and conditions. The terms and conditions pertaining to the software
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* and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
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* (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
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* if applicable the software license agreement. Do not use this software and/or
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* documentation unless you have carefully read and you agree to the limited terms and
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* conditions. By using this software and/or documentation, you agree to the limited
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* terms and conditions.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
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* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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* @endinternal
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*
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* @ingroup rfAna
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*
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* @details
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*
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* <h1> Reference document(s) </h1>
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*/
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/*************************************************************************************************
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* *
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* Header files *
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* *
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*************************************************************************************************/
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#include "memory_map.h"
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#include "rfAna.h"
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#include "clock.h"
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#ifdef REVA
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#include "test.h"
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#endif
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/*************************************************************************************************
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* *
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* Global variables *
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* *
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*************************************************************************************************/
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/** Rf channel and tx power lookup tables (constant)
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* @details
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*
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* The rf channel table is used to program internal hardware register for different 15.4 rf channels.
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* It has 16 entries corresponding to 16 15.4 channels.
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* Entry 1 <-> Channel 11
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* ...
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* Entry 16 <-> Channel 26
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*
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* Each entry is compound of 4 items.
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* Item 0: Rx Frequency integer divide portion
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* Item 1: Rx Frequency fractional divide portion
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* Item 2: Tx Frequency integer divide portion
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* Item 3: Tx Frequency fractional divide portion
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*
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* The tx power table is used to program internal hardware register for different 15.4 tx power levels.
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* It has 43 entries corresponding to tx power levels from -32dBm to +10dBm.
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* Entry 1 <-> -32dB
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* Entry 2 <-> -31dB
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* ...
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* Entry 2 <-> 9dB
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* Entry 43 <-> +10dB
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*
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* Each entry is compound of 1 byte.
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*/
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// RR: Making high side injection changes to RevD
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#ifdef REVD
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/** This rf LUT is built for high side injection, using low side injection
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* would requiere to change this LUT. */
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const uint32_t rfLut[16][4] = {{0x50,0x00D4A7,0x4B,0x00A000},
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{0x50,0x017F52,0x4B,0x014001},
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{0x51,0xFE29FB,0x4B,0x01E001},
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{0x51,0xFED4A6,0x4C,0xFE7FFF},
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{0x51,0xFF7F51,0x4C,0xFF1FFF},
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{0x51,0x0029FC,0x4C,0xFFC000},
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{0x51,0x00D4A7,0x4C,0x006000},
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{0x51,0x017F52,0x4C,0x010001},
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{0x52,0xFE29FB,0x4C,0x01A001},
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{0x52,0xFED4A6,0x4D,0xFE3FFF},
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{0x52,0xFF7F51,0x4D,0xFEDFFF},
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{0x52,0x0029FC,0x4D,0xFF8000},
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{0x52,0x00D4A7,0x4D,0x002000},
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{0x52,0x017F52,0x4D,0x00C001},
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{0x53,0xFE29FB,0x4D,0x016001},
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{0x53,0xFED4A6,0x4E,0xFDFFFE}
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};
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const uint8_t txPowerLut[43] = {0,0,0, // -32dBm to -30dBm
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0,0,0,0,0,0,0,0,0,0, // -29dBm to -20dBm
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0,0,0,0,0,0,0,0,1,2, // -19dBm to -10dBm
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3,4,5,6,7,8,9,10,11,12, // -9dBm to 0dBm
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13,14,15,16,17,18,19,20,20,20
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}; // +1dBm to +10 dBm
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#endif /* REVD */
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#ifdef REVC
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/** This rf LUT is built for low side injection, using high side injection
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* would requiere to change this LUT. */
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const uint32_t rfLut[16][4] = {{0x47,0xFF15FC,0x4B,0x00A000},
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{0x47,0xFFAC93,0x4B,0x014001},
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{0x47,0x00432A,0x4B,0x01E001},
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{0x47,0x00D9C1,0x4C,0xFE7FFF},
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{0x47,0x017058,0x4C,0xFF1FFF},
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{0x48,0xFE06EC,0x4C,0xFFC000},
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{0x48,0xFE9D83,0x4C,0x006000},
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{0x48,0xFF341A,0x4C,0x010001},
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{0x48,0xFFCAB1,0x4C,0x01A001},
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{0x48,0x006148,0x4D,0xFE3FFF},
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{0x48,0x00F7DF,0x4D,0xFEDFFF},
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{0x48,0x018E76,0x4D,0xFF8000},
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{0x49,0xFE250A,0x4D,0x002000},
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{0x49,0xFEBBA1,0x4D,0x00C001},
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{0x49,0xFF5238,0x4D,0x016001},
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{0x49,0xFFE8CF,0x4E,0xFDFFFE}
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};
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const uint8_t txPowerLut[43] = {0,0,0, // -32dBm to -30dBm
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0,0,0,0,0,0,0,0,0,0, // -29dBm to -20dBm
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0,0,0,0,0,0,1,1,2,2, // -19dBm to -10dBm (clamp low at -14dB)
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3,3,4,6,7,9,10,12,13,15, // -9dBm to 0dBm
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17,19,20,20,20,20,20,20,20,20
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}; // +1dBm to +10 dBm (clamp high at +3dB)
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#endif /* REVC */
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#ifdef REVB
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/** This rf LUT is built for low side injection, using high side injection
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* would requiere to change this LUT. */
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const uint32_t rfLut[16][4] = {{0x47,0xFF15FC,0x4B,0x00A000},
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{0x47,0xFFAC93,0x4B,0x014001},
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{0x47,0x00432A,0x4B,0x01E001},
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{0x47,0x00D9C1,0x4C,0xFE7FFF},
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{0x47,0x017058,0x4C,0xFF1FFF},
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{0x48,0xFE06EC,0x4C,0xFFC000},
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{0x48,0xFE9D83,0x4C,0x006000},
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{0x48,0xFF341A,0x4C,0x010001},
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{0x48,0xFFCAB1,0x4C,0x01A001},
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{0x48,0x006148,0x4D,0xFE3FFF},
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{0x48,0x00F7DF,0x4D,0xFEDFFF},
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{0x48,0x018E76,0x4D,0xFF8000},
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{0x49,0xFE250A,0x4D,0x002000},
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{0x49,0xFEBBA1,0x4D,0x00C001},
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{0x49,0xFF5238,0x4D,0x016001},
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{0x49,0xFFE8CF,0x4E,0xFDFFFE}
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};
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const uint8_t txPowerLut[43] = {0,0,0, // -32dBm to -30dBm
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0,0,0,0,0,0,0,0,0,0, // -29dBm to -20dBm
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0,0,0,0,0,0,1,1,2,2, // -19dBm to -10dBm (clamp low at -14dB)
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3,3,4,6,7,9,10,12,13,15, // -9dBm to 0dBm
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17,19,20,20,20,20,20,20,20,20
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}; // +1dBm to +10 dBm (clamp high at +3dB)
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#endif
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#ifdef REVA
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const uint32_t rfLut[16][4] = {{0x57,0xFF5D2F,0x51,0x018001},
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{0x57,0x0007DA,0x52,0xFE1FFF},
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{0x57,0x00B285,0x52,0xFEBFFF},
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{0x57,0x015D30,0x52,0xFF6000},
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{0x58,0xFE07D8,0x52,0x000000},
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{0x58,0xFEB283,0x52,0x00A000},
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{0x58,0xFF5D2F,0x52,0x014001},
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{0x58,0x0007DA,0x52,0x01E001},
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{0x58,0x00B285,0x53,0xFE7FFF},
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{0x58,0x015D30,0x53,0xFF1FFF},
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{0x59,0xFE07D8,0x53,0xFFC000},
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{0x59,0xFEB283,0x53,0x006000},
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{0x59,0xFF5D2F,0x53,0x010001},
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{0x59,0x0007DA,0x53,0x01A001},
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{0x59,0x00B285,0x53,0xFE3FFF},
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{0x59,0x015D30,0x53,0xFEDFFF}
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};
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const uint8_t txPowerLut[43] = {1,2,3, // -32dBm to -30dBm
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4,5,5,5,5,5,5,5,5,5, // -29dBm to -20dBm (clamp at -28dB)
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5,5,5,5,5,5,5,5,5,5, // -19dBm to -10dBm
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5,5,5,5,5,5,5,5,5,5, // -9dBm to 0dBm
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5,5,5,5,5,5,5,5,5,5
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}; // +1dBm to +10 dBm
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#endif
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/*************************************************************************************************
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* *
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* Functions *
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* *
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*************************************************************************************************/
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void fRfAnaInit()
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{
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// Enable rfana clock
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CLOCK_ENABLE(CLOCK_RFANA);
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#ifdef REVA
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// Force Pll lock (it shouldn't be needed for either silicon if the part is configured/trimmed properly)
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fTestForcePllLock();
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// Bypass Pll regulator
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fTestBypassPllReg();
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#endif
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// Set PLL timing
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RFANAREG->PLL_TIMING.BITS.PLL_RESET_TIME = 0x1E; // 30us
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RFANAREG->PLL_TIMING.BITS.PLL_LOCK_TIME = 0x2F; // 47us
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// Set other parameters
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RFANAREG->RX_CONTROL.BITS.LNA_GAIN_MODE = 0x1; // High Gain mode
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RFANAREG->RX_CONTROL.BITS.ADC_DITHER_MODE = 0x0; // Dither mode disabled
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}
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boolean fRfAnaIoctl (uint32_t request, void *argument)
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{
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uint8_t channel, txPower;
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// Enable rfana clock (in case fRfAnaIoctl is used before call of fRfAnaInit)
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CLOCK_ENABLE(CLOCK_RFANA);
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switch(request) {
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case SET_RF_CHANNEL:
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channel = *(uint8_t*)argument;
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// Set tx/rx integer/fractional divide portions
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RFANAREG->TX_LO_CONTROL.BITS.FRACT_WORD = rfLut[channel - 11][3];
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RFANAREG->TX_LO_CONTROL.BITS.INT_WORD = rfLut[channel - 11][2];
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RFANAREG->RX_LO_CONTROL.BITS.FRACT_WORD = rfLut[channel - 11][1];
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RFANAREG->RX_LO_CONTROL.BITS.INT_WORD = rfLut[channel - 11][0];
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// Set tx/rx vco trims
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#ifdef REVB
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/** REVB is requiering to adjust tx/rx vco trims each time a new 15.4 channel is used, in revB it is done
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* from trims stored in flash A, it has the drawback that it is not workable when flash A is not accessible.*/
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if (channel < 19) {
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RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (TRIMREG->TX_VCO_LUT1.WORD) >> ((channel - 11) * 4);
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RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (TRIMREG->RX_VCO_LUT1.WORD) >> ((channel - 11) * 4);
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} else {
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RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (TRIMREG->TX_VCO_LUT2.WORD) >> ((channel - 19) * 4);
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RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (TRIMREG->RX_VCO_LUT2.WORD) >> ((channel - 19) * 4);
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}
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#endif /* REVB */
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#ifdef REVC
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/** REVC is requiering to adjust tx/rx vco trims each time a new 15.4 channel is used, in revB it is done
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* from trims stored in dedicated registers available in digital.*/
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if (channel < 19) {
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RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
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RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
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} else {
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RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
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RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
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}
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#endif /* REVC */
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#ifdef REVD
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/** REVD is requiering to adjust tx/rx vco trims each time a new 15.4 channel is used, in revB it is done
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* from trims stored in dedicated registers available in digital.*/
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if (channel < 19) {
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RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
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RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
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} else {
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RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
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RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
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}
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#endif /* REVD */
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break;
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case SET_TX_POWER:
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txPower = *(uint8_t*)argument;
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// Set tx power register
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if ((txPower & 0x20) == 0) {
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RFANAREG->TX_POWER = (txPowerLut[txPower + 32] & 0xFF);
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} else {
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RFANAREG->TX_POWER = (txPowerLut[txPower - 32] & 0xFF);
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}
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break;
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default:
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return False;
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}
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return True;
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}
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