mirror of https://github.com/ARMmbed/mbed-os.git
84 lines
3.2 KiB
C
84 lines
3.2 KiB
C
/* mbed Microcontroller Library
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* Copyright (c) 2006-2015 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "sleep_api.h"
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#include "cmsis.h"
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//Normal wait mode
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void hal_sleep(void)
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{
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SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
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//Normal sleep mode for ARM core:
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SCB->SCR = 0;
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__WFI();
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}
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//Very low-power stop mode
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void hal_deepsleep(void)
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{
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//Check if ADC is enabled and HS mode is set, if yes disable it (lowers power consumption by 60uA)
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uint8_t ADC_HSC = 0;
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if (SIM->SCGC6 & SIM_SCGC6_ADC0_MASK) {
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if (ADC0->CFG2 & ADC_CFG2_ADHSC_MASK) {
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ADC_HSC = 1;
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ADC0->CFG2 &= ~(ADC_CFG2_ADHSC_MASK);
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}
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}
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//Check if PLL/FLL is enabled:
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uint32_t PLL_FLL_en = (MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0);
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SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
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SMC->PMCTRL = SMC_PMCTRL_STOPM(2);
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//Deep sleep for ARM core:
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SCB->SCR = 1<<SCB_SCR_SLEEPDEEP_Pos;
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__WFI();
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//Switch back to PLL as clock source if needed
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//The interrupt that woke up the device will run at reduced speed
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if (PLL_FLL_en) {
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#if defined (TARGET_K20D50M)
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if (MCG->C6 & (1<<MCG_C6_PLLS_SHIFT) != 0) /* If PLL */
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while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U); /* Wait until locked */
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MCG->C1 &= ~MCG_C1_CLKS_MASK;
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#else
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// MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0
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MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
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// MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0
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MCG->C6 = MCG_C6_VDIV0(0);
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while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } // Check that the oscillator is running
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while((MCG->S & 0x0Cu) != 0x08u) { } // Wait until external reference clock is selected as MCG output
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// MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=3
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MCG->C5 = MCG_C5_PRDIV0(5);
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// MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=3
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MCG->C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(3);
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while((MCG->S & 0x0Cu) != 0x08u) { } // Wait until external reference clock is selected as MCG output
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while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } // Wait until the source of the PLLS clock has switched to the PLL
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while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } // Wait until locked
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// MCG->C1: CLKS=0,FRDIV=2,IREFS=0,IRCLKEN=1,IREFSTEN=0
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MCG->C1 = MCG_C1_FRDIV(2) | MCG_C1_IRCLKEN_MASK;;
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while((MCG->S & 0x0Cu) != 0x0Cu) { } // Wait until output of the PLL is selected
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while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } // Wait until locked
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#endif
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}
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if (ADC_HSC) {
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ADC0->CFG2 |= (ADC_CFG2_ADHSC_MASK);
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}
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}
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