mirror of https://github.com/ARMmbed/mbed-os.git
116 lines
4.3 KiB
C
116 lines
4.3 KiB
C
/* mbed Microcontroller Library
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* Copyright (c) 2006-2015 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef CLK_FREQS_H
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#define CLK_FREQS_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*!
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* \brief Get the peripheral bus clock frequency
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* \return Bus frequency
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*/
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static inline uint32_t bus_frequency(void) {
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return SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT) + 1);
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}
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/*!
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* \brief Get external oscillator (crystal) frequency
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* \return External osc frequency
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*/
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static uint32_t extosc_frequency(void) {
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uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
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if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(2)) //MCG clock = external reference clock
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return MCGClock;
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if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0)) { //PLL/FLL is selected
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uint32_t divider, multiplier;
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if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
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if ((MCG->S & MCG_S_IREFST_MASK) == 0x0u) { //FLL uses external reference
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divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
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if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u)
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divider <<= 5u;
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/* Select correct multiplier to calculate the MCG output clock */
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switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
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case 0x0u:
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multiplier = 640u;
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break;
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case 0x20u:
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multiplier = 1280u;
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break;
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case 0x40u:
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multiplier = 1920u;
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break;
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case 0x60u:
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multiplier = 2560u;
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break;
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case 0x80u:
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multiplier = 732u;
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break;
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case 0xA0u:
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multiplier = 1464u;
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break;
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case 0xC0u:
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multiplier = 2197u;
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break;
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case 0xE0u:
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default:
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multiplier = 2929u;
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break;
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}
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return MCGClock * divider / multiplier;
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}
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} else { //PLL is selected
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divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
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multiplier = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
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return MCGClock * divider / multiplier;
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}
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}
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//In all other cases either there is no crystal or we cannot determine it
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//For example when the FLL is running on the internal reference, and there is also an
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//external crystal. However these are unlikely situations
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return 0;
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}
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//Get MCG PLL/2 or FLL frequency, depending on which one is active, sets PLLFLLSEL bit
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static uint32_t mcgpllfll_frequency(void) {
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if ((MCG->C1 & MCG_C1_CLKS_MASK) != MCG_C1_CLKS(0)) //PLL/FLL is not selected
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return 0;
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uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
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if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
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SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is FLL output
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return MCGClock;
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} else { //PLL is selected
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SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is PLL output
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return MCGClock;
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}
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//It is possible the SystemCoreClock isn't running on the PLL, and the PLL is still active
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//for the peripherals, this is however an unlikely setup
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}
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#ifdef __cplusplus
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}
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#endif
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#endif
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