mirror of https://github.com/ARMmbed/mbed-os.git
99 lines
8.5 KiB
XML
99 lines
8.5 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<!--****************************************************************************
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* \file sysanalog.cypersonality
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* \version 1.0
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*
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* \brief
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* SysAnalog personality description file.
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*
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********************************************************************************
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* \copyright
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* Copyright 2018-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*****************************************************************************-->
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<Personality id="mxs40sysanalog" name="Programmable Analog" version="1.0" path="Analog" xmlns="http://cypress.com/xsd/cyhwpersonality_v1">
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<Dependencies>
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<IpBlock name="mxs40pass" />
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<Resource name="pass" used="true" />
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<DependentResource name="pass.ctb.oa" />
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</Dependencies>
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<ExposedMembers>
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<ExposedMember key="iptat_level" paramId="iptat_level" />
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<ExposedMember key="ctb0_deep_sleep" paramId="ctb0_deep_sleep" />
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<ExposedMember key="ctb1_deep_sleep" paramId="ctb1_deep_sleep" />
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<ExposedMember key="ctb2_deep_sleep" paramId="ctb2_deep_sleep" />
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<ExposedMember key="ctb3_deep_sleep" paramId="ctb3_deep_sleep" />
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<ExposedMember key="pump_clk_freq_hz" paramId="pump_clk_freq_hz" />
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</ExposedMembers>
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<Parameters>
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<!-- PDL documentation -->
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<ParamDoc id="pdlDoc" name="Configuration Help" group="Peripheral Documentation" default="file:///`${cy_libs_path()}`/docs/pdl_api_reference_manual/html/group__group__ctb.html" linkText="Open CTB Documentation" visible="true" desc="Opens the Peripheral Driver Library Documentation" />
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<!--Internal-->
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<ParamBool id="isClkPumpEnabled" name="Is Pump Clock Enabled" group="Internal" default="`${isBlockUsed("srss[0].clock[0].pumpclk[0]")}`" visible="false" editable="false" desc="Pump clock enabling state" />
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<ParamBool id="hasCTB" name="hasCTB" group="Internal" default="`${hasBlock("pass[0].ctb[0].oa[0]")}`" visible="false" editable="false" desc="Check whether device has CTBs" />
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<ParamBool id="isArefEnabled" name="Is Aref Enabled" group="Internal" default="`${isBlockUsed("pass[0].aref[0]")}`" visible="false" editable="false" desc="" />
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<!--Internal-->
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<ParamChoice id="iptat_level" name="Opamp Reference Current" group="Global Opamp Settings" default="CY_CTB_IPTAT_NORMAL" visible="`${hasCTB}`" editable="true" desc="Select the level for the opamp current output." >
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<Entry name="1 uA" value="CY_CTB_IPTAT_NORMAL" visible="true" />
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<Entry name="100 nA" value="CY_CTB_IPTAT_LOW" visible="true" />
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</ParamChoice>
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<ParamChoice id="pump_clock_source" name="Opamp Pump Clock Source" group="Global Opamp Settings" default="CY_CTB_CLK_PUMP_SRSS" visible="`${hasCTB}`" editable="true" desc="Select the clock source for the opamp pump clock." >
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<Entry name="SRSS" value="CY_CTB_CLK_PUMP_SRSS" visible="true" />
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<Entry name="Peri Clock Divider" value="CY_CTB_CLK_PUMP_PERI" visible="true" />
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</ParamChoice>
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<ParamSignal name="Peri Clock" port="clock_pump_peri[0]" group="Global Opamp Settings" visible="`${pump_clock_source eq CY_CTB_CLK_PUMP_PERI}`" desc="Peri divider clock for the pump clock." canBeEmpty="`${pump_clock_source eq CY_CTB_CLK_PUMP_SRSS}`" />
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<ParamString id="peri_source_clock" name="Pump Clock Peri Source Resource" group="Global Opamp Settings" default="`${getBlockFromSignal("clock_pump_peri[0]")}`" visible="false" editable="false" desc="Pump Clock Peri Source Resource" />
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<ParamRange id="pump_clk_freq_hz" name="Frequency" group="Internal" default="`${(pump_clock_source eq CY_CTB_CLK_PUMP_SRSS) ? (isClkPumpEnabled ? getExposedMember("srss[0].clock[0].pumpclk[0]", "frequency") : 0) : ((peri_source_clock ne "") ? getExposedMember(peri_source_clock, "frequency") : 0)}`" min="0" max="1000000000" resolution="1" visible="false" editable="false" desc=""/>
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<ParamString id="pump_clk_freq" name="Opamp Pump Clock Frequency" group="Global Opamp Settings" default="`${pump_clk_freq_hz < 1000000 ? pump_clk_freq_hz / 1000.0 . " kHz" : pump_clk_freq_hz / 1000000.0 . " MHz"}`" visible="`${hasCTB}`" editable="false" desc="Frequency of the Analog Pump Clock" />
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<ParamBool id="ctb0_deep_sleep" name="Deep Sleep Enable" group="CTB0" default="false" visible="`${hasCTB && (NR_CTBS > 0)}`" editable="true" desc="Maintain the opamp output during Deep Sleep for CTB0. Enabling Deep Sleep will reduce the output range of the opamp." />
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<ParamBool id="ctb1_deep_sleep" name="Deep Sleep Enable" group="CTB1" default="false" visible="`${hasCTB && (NR_CTBS > 1)}`" editable="true" desc="Maintain the opamp output during Deep Sleep for CTB1. Enabling Deep Sleep will reduce the output range of the opamp." />
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<ParamBool id="ctb2_deep_sleep" name="Deep Sleep Enable" group="CTB2" default="false" visible="`${hasCTB && (NR_CTBS > 2)}`" editable="true" desc="Maintain the opamp output during Deep Sleep for CTB2. Enabling Deep Sleep will reduce the output range of the opamp." />
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<ParamBool id="ctb3_deep_sleep" name="Deep Sleep Enable" group="CTB3" default="false" visible="`${hasCTB && (NR_CTBS > 3)}`" editable="true" desc="Maintain the opamp output during Deep Sleep for CTB3. Enabling Deep Sleep will reduce the output range of the opamp." />
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<!-- Peripheral clock divider connection -->
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<ParamString id="pclk" name="PCLK" group="Internal" default="`${getBlockFromSignal("clock_pump_peri[0]")}`" visible="false" editable="false" desc="Connected peripheral clock divider (PCLK)." />
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<ParamBool id="pclkOk" name="PCLK Valid" group="Internal" default="`${hasConnection("clock_pump_peri", 0) && isBlockUsed(pclk)}`" visible="false" editable="false" desc="Checks whether there is a PCLK connected and enabled." />
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<ParamString id="pclkDst" name="PCLK Destination" group="Internal" default="PCLK_PASS_CLOCK_PUMP_PERI" visible="false" editable="false" desc="Generates PCLK connection define." />
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</Parameters>
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<DRCs>
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<DRC type="ERROR" text="Pump clock (CLK_PUMP) resource must be enabled when the Opamp Pump Clock Source is set to SRSS." condition="`${hasCTB && !isClkPumpEnabled && pump_clock_source eq CY_CTB_CLK_PUMP_SRSS}`" location="srss[0].clock[0].pumpclk[0]">
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<FixIt action="ENABLE_BLOCK" target="srss[0].clock[0].pumpclk[0]" value="mxs40pumpclk-1.0" valid="true" />
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</DRC>
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</DRCs>
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<ConfigFirmware>
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<ConfigInclude value="cy_ctb.h" include="`${iptat_level eq CY_CTB_IPTAT_LOW}`" />
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<ConfigInclude value="cy_sysclk.h" include="`${pclkOk}`" />
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<ConfigInstruction value="Cy_CTB_SetIptatLevel(`${iptat_level}`);" include="`${iptat_level eq CY_CTB_IPTAT_LOW}`" />
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<ConfigInstruction value="Cy_SysClk_PeriphAssignDivider(`${pclkDst}`, `${getExposedMember(pclk, "clockSel")}`);" include="`${pump_clock_source eq CY_CTB_CLK_PUMP_PERI && pclkOk}`" />
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<ConfigInstruction value="Cy_CTB_SetDeepSleepMode(CTBM0, `${ctb0_deep_sleep ? "CY_CTB_DEEPSLEEP_ENABLE" : "CY_CTB_DEEPSLEEP_DISABLE"}`);" include="`${isBlockUsed("pass[0].ctb[0].oa[0]") || isBlockUsed("pass[0].ctb[0].oa[1]")}`"/>
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<ConfigInstruction value="Cy_CTB_SetDeepSleepMode(CTBM1, `${ctb1_deep_sleep ? "CY_CTB_DEEPSLEEP_ENABLE" : "CY_CTB_DEEPSLEEP_DISABLE"}`);" include="`${isBlockUsed("pass[0].ctb[1].oa[0]") || isBlockUsed("pass[0].ctb[1].oa[1]")}`"/>
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<ConfigInstruction value="Cy_CTB_SetDeepSleepMode(CTBM2, `${ctb2_deep_sleep ? "CY_CTB_DEEPSLEEP_ENABLE" : "CY_CTB_DEEPSLEEP_DISABLE"}`);" include="`${isBlockUsed("pass[0].ctb[2].oa[0]") || isBlockUsed("pass[0].ctb[2].oa[1]")}`"/>
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<ConfigInstruction value="Cy_CTB_SetDeepSleepMode(CTBM3, `${ctb3_deep_sleep ? "CY_CTB_DEEPSLEEP_ENABLE" : "CY_CTB_DEEPSLEEP_DISABLE"}`);" include="`${isBlockUsed("pass[0].ctb[3].oa[0]") || isBlockUsed("pass[0].ctb[3].oa[1]")}`"/>
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</ConfigFirmware>
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</Personality>
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