mirror of https://github.com/ARMmbed/mbed-os.git
135 lines
6.5 KiB
C
135 lines
6.5 KiB
C
/* mbed Microcontroller Library
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* Copyright (c) 2015 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/*
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* SSP interface Support
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* =====================
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*/
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#ifndef MBED_SPI_DEF_H
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#define MBED_SPI_DEF_H
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#include <stdint.h> /* standard types definitions */
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#define Module_ID 0x00090108
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typedef struct beetle_spi
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{
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__IO uint32_t CONFIG; /* 0x00 RW Configuration Register */
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__I uint32_t IRQ_STATUS; /* 0x04 RO Interrupt Status Register*/
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__O uint32_t IRQ_ENABLE; /* 0x08 WO Interrupt Enable Register*/
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__O uint32_t IRQ_DISABLE; /* 0x0C WO Interrupt Disable Register */
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__I uint32_t IRQ_MASK; /* 0x10 RO Interrupt Mask Register */
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__IO uint32_t SPI_ENABLE; /* 0x14 RW SPI Enable Register */
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__IO uint32_t DELAY; /* 0x18 RW Delay Register */
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__O uint32_t TX_DATA; /* 0x1C WO Transmit Data Register */
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__I uint32_t RX_DATA; /* 0x20 RO Receive Data Register */
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__IO uint32_t SLAVE_IDLE_COUNT; /* 0x24 RW Slave Idle Count Register */
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__IO uint32_t TX_THRESHOLD; /* 0x28 RW TX Threshold Register */
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__IO uint32_t RX_THRESHOLD; /* 0x2C RW RX Threshold Register */
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uint32_t reserved[208];
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__I uint32_t MID; /* 0xFC RO Module ID Register */
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}SPI_TypeDef;
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#define SPI0_BASE (0x4000C000ul) /* Shield Header SPI Base Address */
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#define SPI1_BASE (0x4000D000ul) /* ADC SPI Base Address */
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#define SHIELD_SPI ((SPI_TypeDef *) SPI0_BASE )
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#define ADC_SPI ((SPI_TypeDef *) SPI1_BASE )
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/* Configuration Register Bit Masks */
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#define CONFIG_MSEL 0x00001 // Bit [00] MSEL Mode Select
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#define CONFIG_CPOL 0x00002 // Bit [01] CPOL External Clock Edge
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#define CONFIG_CPHA 0x00004 // Bit [02] CPHA Clock Phase
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#define CONFIG_MBRD 0x00038 // Bits [05:03] MBRD Master Baud Rate Divisor (2 to 256)
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#define CONFIG_MBRD_0 0x00008
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#define CONFIG_MBRD_1 0x00010
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#define CONFIG_MBRD_2 0x00020
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#define CONFIG_MBRD_SHIFT 3
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#define CONFIG_TWS 0x000C0 // Bits [07:06] TWS Transfer Word Size
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#define CONFIG_TWS_0 0x00000
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#define CONFIG_TWS_1 0x00040
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#define CONFIG_MRCS 0x00100 // Bit [08] MRCS Reference Clock Select
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#define CONFIG_PSD 0x00200 // Bit [09] PSD Peripheral Select Decode
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#define CONFIG_PCSL 0x03C00 // Bits [13:10] PCSL Peripheral Chip Select Lines (master mode only)
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#define CONFIG_MCSE 0x04000 // Bit [14] MCSE Manual Chip Select Enable
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#define CONFIG_MSE 0x08000 // Bit [15] MSE Manual Start Enable
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#define CONFIG_MSC 0x10000 // Bit [16] MSC Manual Start Command
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#define CONFIG_MFGE 0x20000 // Bit [17] MFGE Mode Fail Generation Enable
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#define CONFIG_SPSE 0x40000 // Bit [18] SPSE Sample Point Shift Enable
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/* Interrupt Status Register Bit Masks */
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#define IRQ_STATUS_ROF 0x01 // Bit [00] ROF RX FIFO Overflow
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#define IRQ_STATUS_MF 0x02 // Bit [01] MF Mode Fail
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#define IRQ_STATUS_TNF 0x04 // Bit [02] TNF TX FIFO Not Full (current FIFO status)
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#define IRQ_STATUS_TF 0x08 // Bit [03] TF TX FIFO Full (current FIFO status)
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#define IRQ_STATUS_RNE 0x10 // Bit [04] RNE RX FIFO Not Empty (current FIFO status)
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#define IRQ_STATUS_RF 0x20 // Bit [05] RF RX FIFO Full (current FIFO status)
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#define IRQ_STATUS_TUF 0x40 // Bit [06] TUF TX FIFO Underflow
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/* Interrupt Enable Register Bit Masks */
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#define IRQ_ENABLE_ROFE 0x01 // Bit [00] ROFE RX FIFO Overflow Enable
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#define IRQ_ENABLE_MFE 0x02 // Bit [01] MFE Mode Fail Enable
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#define IRQ_ENABLE_TNFE 0x04 // Bit [02] TNFE TX FIFO Not Full Enable
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#define IRQ_ENABLE_TFE 0x08 // Bit [03] TFE TX FIFO Full Enable
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#define IRQ_ENABLE_RNEE 0x10 // Bit [04] RNEE RX FIFO Not Empty Enable
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#define IRQ_ENABLE_RFE 0x20 // Bit [05] RFE RX FIFO Full Enable
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#define IRQ_ENABLE_TUFE 0x40 // Bit [06] TUFE TX FIFO Underflow Enable
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/* Interrupt Disable Register Bit Masks */
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#define IRQ_DISABLE_ROFD 0x01 // Bit [00] ROFD RX FIFO Overflow Disable
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#define IRQ_DISABLE_MFD 0x02 // Bit [01] MFD Mode Fail Disable
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#define IRQ_DISABLE_TNFD 0x04 // Bit [02] TNFD TX FIFO Not Full Disable
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#define IRQ_DISABLE_TFD 0x08 // Bit [03] TFD TX FIFO Full Disable
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#define IRQ_DISABLE_RNED 0x10 // Bit [04] RNED RX FIFO Not Empty Disable
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#define IRQ_DISABLE_RFD 0x20 // Bit [05] RFD RX FIFO Full Disable
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#define IRQ_DISABLE_TUFD 0x40 // Bit [06] TUFD TX FIFO Underflow Disable
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/* Interrupt Mask Register Bit Masks */
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#define IRQ_MASK_ROFM 0x01 // Bit [00] ROFM RX FIFO Overflow Mask
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#define IRQ_MASK_MFM 0x02 // Bit [01] MFM Mode Fail Mask
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#define IRQ_MASK_TNFM 0x04 // Bit [02] TNFM TX FIFO Not Full Mask
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#define IRQ_MASK_TFM 0x08 // Bit [03] TFM TX FIFO Full Mask
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#define IRQ_MASK_RNEM 0x10 // Bit [04] RNEM RX FIFO Not Empty Mask
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#define IRQ_MASK_RFM 0x20 // Bit [05] RFM RX FIFO Full Mask
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#define IRQ_MASK_TUFM 0x40 // Bit [06] TUFM TX FIFO Underflow Mask
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/* SPI Enable Register Bit Masks */
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#define SPI_ENABLE_SPIE 0x01 // Bit [00] SPIE SPI Enable
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/* Delay Register Bit Masks */
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#define DELAY_D_INIT 0x000000FF // Bits [07:00] D_INIT Delay Init
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#define DELAY_D_AFTER 0x0000FF00 // Bits [15:08] D_AFTER Delay After
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#define DELAY_D_BTWN 0x00FF0000 // Bits [23:16] D_BTWN Delay Between
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#define DELAY_D_NSS 0xFF000000 // Bits [31:24] D_NSS Delay NSS
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/* Transmit Data Register Bit Masks */
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#define TX_DATA_TDATA 0xFF
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/* Receive Data Register Bit Masks */
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#define RX_DATA_RDATA 0xFF
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/* Slave Idle Count Register Bit Masks */
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#define SLAVE_IDLE_COUNT_SICNT 0xFF // Bits [07:00] SICNT Slave Idle Count
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/* TX Threshold Register Bit Masks */
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#define TX_THRESHOLD_TTRSH 0x07 // Bits [N:00] TTRSH TX Threshold
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/* RX Threshold Register Bit Masks */
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#define RX_THRESHOLD_RTRSH 0x07 // Bits [N:00] RTRSH RX Threshold
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#endif
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