mirror of https://github.com/ARMmbed/mbed-os.git
400 lines
9.7 KiB
C
400 lines
9.7 KiB
C
/* mbed Microcontroller Library
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* Copyright (c) 2015 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <stddef.h>
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#include "cmsis.h"
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#include "gpio_irq_api.h"
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#include "mbed_error.h"
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#define CHANNEL_NUM 32
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#define CMSDK_GPIO_0 CMSDK_GPIO0
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#define CMSDK_GPIO_1 CMSDK_GPIO1
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#define PININT_IRQ 0
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static uint32_t channel_ids[CHANNEL_NUM] = {0};
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static gpio_irq_handler irq_handler;
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static inline void handle_interrupt_in(uint32_t channel) {
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uint32_t ch_bit = (1 << channel);
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// Return immediately if:
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// * The interrupt was already served
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// * There is no user handler
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// * It is a level interrupt, not an edge interrupt
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if (ch_bit <16){
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if (((CMSDK_GPIO_0->INTSTATUS) == 0) || (channel_ids[channel] == 0)
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|| ((CMSDK_GPIO_0->INTTYPESET) == 0))
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return;
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if ((CMSDK_GPIO_0->INTTYPESET & ch_bit)
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&& (CMSDK_GPIO_0->INTPOLSET & ch_bit)) {
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irq_handler(channel_ids[channel], IRQ_RISE);
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CMSDK_GPIO_0->INTPOLSET = ch_bit;
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}
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if ((CMSDK_GPIO_0->INTTYPESET & ch_bit)
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&& ~(CMSDK_GPIO_0->INTPOLSET & ch_bit)) {
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irq_handler(channel_ids[channel], IRQ_FALL);
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}
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CMSDK_GPIO_0->INTCLEAR = ch_bit;
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}
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if (ch_bit>=16) {
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if (((CMSDK_GPIO_1->INTSTATUS) == 0) || (channel_ids[channel] == 0)
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|| ((CMSDK_GPIO_1->INTTYPESET) == 0))
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return;
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if ((CMSDK_GPIO_1->INTTYPESET & ch_bit)
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&& (CMSDK_GPIO_1->INTPOLSET & ch_bit)) {
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irq_handler(channel_ids[channel], IRQ_RISE);
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CMSDK_GPIO_1->INTPOLSET = ch_bit;
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}
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if ((CMSDK_GPIO_1->INTTYPESET & ch_bit)
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&& ~(CMSDK_GPIO_1->INTPOLSET & ch_bit)) {
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irq_handler(channel_ids[channel], IRQ_FALL);
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}
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CMSDK_GPIO_1->INTCLEAR = ch_bit;
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}
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}
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void gpio0_irq0(void) {
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handle_interrupt_in(0);
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}
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void gpio0_irq1(void) {
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handle_interrupt_in(1);
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}
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void gpio0_irq2(void) {
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handle_interrupt_in(2);
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}
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void gpio0_irq3(void) {
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handle_interrupt_in(3);
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}
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void gpio0_irq4(void) {
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handle_interrupt_in(4);
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}
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void gpio0_irq5(void) {
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handle_interrupt_in(5);
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}
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void gpio0_irq6(void) {
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handle_interrupt_in(6);
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}
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void gpio0_irq7(void) {
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handle_interrupt_in(7);
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}
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void gpio0_irq8(void) {
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handle_interrupt_in(8);
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}
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void gpio0_irq9(void) {
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handle_interrupt_in(9);
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}
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void gpio0_irq10(void) {
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handle_interrupt_in(10);
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}
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void gpio0_irq11(void) {
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handle_interrupt_in(11);
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}
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void gpio0_irq12(void) {
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handle_interrupt_in(12);
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}
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void gpio0_irq13(void) {
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handle_interrupt_in(13);
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}
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void gpio0_irq14(void) {
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handle_interrupt_in(14);
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}
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void gpio0_irq15(void) {
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handle_interrupt_in(15);
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}
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void gpio1_irq0(void) {
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handle_interrupt_in(16);
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}
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void gpio1_irq1(void) {
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handle_interrupt_in(17);
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}
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void gpio1_irq2(void) {
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handle_interrupt_in(18);
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}
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void gpio1_irq3(void) {
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handle_interrupt_in(19);
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}
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void gpio1_irq4(void) {
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handle_interrupt_in(20);
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}
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void gpio1_irq5(void) {
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handle_interrupt_in(21);
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}
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void gpio1_irq6(void) {
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handle_interrupt_in(22);
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}
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void gpio1_irq7(void) {
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handle_interrupt_in(23);
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}
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void gpio1_irq8(void) {
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handle_interrupt_in(24);
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}
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void gpio1_irq9(void) {
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handle_interrupt_in(25);
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}
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void gpio1_irq10(void) {
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handle_interrupt_in(26);
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}
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void gpio1_irq11(void) {
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handle_interrupt_in(27);
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}
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void gpio1_irq12(void) {
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handle_interrupt_in(28);
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}
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void gpio1_irq13(void) {
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handle_interrupt_in(29);
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}
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void gpio1_irq14(void) {
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handle_interrupt_in(30);
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}
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void gpio1_irq15(void) {
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handle_interrupt_in(31);
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}
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int gpio_irq_init(gpio_irq_t *obj, PinName pin,
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gpio_irq_handler handler, uint32_t id) {
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if (pin == NC) {return -1;}
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else {
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irq_handler = handler;
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int found_free_channel = 0;
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int i = 0;
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for (i=0; i<CHANNEL_NUM; i++) {
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if (channel_ids[i] == 0) {
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channel_ids[i] = id;
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obj->ch = i;
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found_free_channel = 1;
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break;
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}
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}
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if (!found_free_channel)
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return -1;
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/* To select a pin for any of the eight pin interrupts, write the pin number
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* as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55.
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* @see: mbed_capi/PinNames.h
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*/
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if (pin <16) {
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CMSDK_GPIO_0->INTENSET |= (0x1 << pin);
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}
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if (pin >= 16) {
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CMSDK_GPIO_1->INTENSET |= (0x1 << pin);
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}
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void (*channels_irq)(void) = NULL;
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switch (obj->ch) {
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case 0:
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channels_irq = &gpio0_irq0;
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break;
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case 1:
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channels_irq = &gpio0_irq1;
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break;
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case 2:
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channels_irq = &gpio0_irq2;
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break;
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case 3:
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channels_irq = &gpio0_irq3;
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break;
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case 4:
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channels_irq = &gpio0_irq4;
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break;
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case 5:
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channels_irq = &gpio0_irq5;
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break;
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case 6:
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channels_irq = &gpio0_irq6;
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break;
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case 7:
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channels_irq = &gpio0_irq7;
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break;
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case 8:
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channels_irq = &gpio0_irq8;
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break;
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case 9:
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channels_irq = &gpio0_irq9;
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break;
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case 10:
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channels_irq = &gpio0_irq10;
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break;
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case 11:
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channels_irq = &gpio0_irq11;
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break;
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case 12:
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channels_irq = &gpio0_irq12;
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break;
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case 13:
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channels_irq = &gpio0_irq13;
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break;
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case 14:
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channels_irq = &gpio0_irq14;
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break;
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case 15:
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channels_irq = &gpio0_irq15;
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break;
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case 16:
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channels_irq = &gpio1_irq0;
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break;
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case 17:
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channels_irq = &gpio1_irq1;
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break;
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case 18:
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channels_irq = &gpio1_irq2;
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break;
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case 19:
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channels_irq = &gpio1_irq3;
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break;
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case 20:
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channels_irq = &gpio1_irq4;
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break;
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case 21:
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channels_irq = &gpio1_irq5;
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break;
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case 22:
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channels_irq = &gpio1_irq6;
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break;
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case 23:
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channels_irq = &gpio1_irq7;
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break;
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case 24:
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channels_irq = &gpio1_irq8;
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break;
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case 25:
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channels_irq = &gpio1_irq9;
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break;
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case 26:
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channels_irq = &gpio1_irq10;
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break;
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case 27:
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channels_irq = &gpio1_irq11;
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break;
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case 28:
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channels_irq = &gpio1_irq12;
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break;
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case 29:
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channels_irq = &gpio1_irq13;
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break;
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case 30:
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channels_irq = &gpio1_irq14;
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break;
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case 31:
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channels_irq = &gpio1_irq15;
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break;
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}
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NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch),
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(uint32_t)channels_irq);
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NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
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return 0;
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}
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}
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void gpio_irq_free(gpio_irq_t *obj) {
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}
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void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
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unsigned int ch_bit = (1 << obj->ch);
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// Clear interrupt
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if (obj->ch <16) {
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if (!(CMSDK_GPIO_0->INTTYPESET & ch_bit)) {
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CMSDK_GPIO_0->INTCLEAR = ch_bit;
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}
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}
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if (obj->ch >= 16) {
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if (!(CMSDK_GPIO_1->INTTYPESET & ch_bit)) {
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CMSDK_GPIO_1->INTCLEAR = ch_bit;
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}
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}
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// Edge trigger
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if (obj->ch <16) {
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CMSDK_GPIO_0->INTTYPESET &= ch_bit;
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if (event == IRQ_RISE) {
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CMSDK_GPIO_0->INTPOLSET |= ch_bit;
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if (enable) {
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CMSDK_GPIO_0->INTENSET |= ch_bit;
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} else {
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CMSDK_GPIO_0->INTENCLR |= ch_bit;
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}
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} else {
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CMSDK_GPIO_0->INTPOLCLR |= ch_bit;
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if (enable) {
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CMSDK_GPIO_0->INTENSET |= ch_bit;
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} else {
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CMSDK_GPIO_0->INTENCLR |= ch_bit;
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}
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}
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}
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if (obj->ch >= 16) {
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CMSDK_GPIO_1->INTTYPESET &= ch_bit;
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if (event == IRQ_RISE) {
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CMSDK_GPIO_1->INTPOLSET |= ch_bit;
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if (enable) {
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CMSDK_GPIO_1->INTENSET |= ch_bit;
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} else {
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CMSDK_GPIO_1->INTENCLR |= ch_bit;
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}
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} else {
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CMSDK_GPIO_1->INTPOLCLR |= ch_bit;
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if (enable) {
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CMSDK_GPIO_1->INTENSET |= ch_bit;
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} else {
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CMSDK_GPIO_1->INTENCLR |= ch_bit;
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}
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}
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}
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}
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void gpio_irq_enable(gpio_irq_t *obj) {
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NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
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}
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void gpio_irq_disable(gpio_irq_t *obj) {
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NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
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}
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