mirror of https://github.com/ARMmbed/mbed-os.git
230 lines
6.5 KiB
C
230 lines
6.5 KiB
C
/**
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*******************************************************************************
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* @file spi_api.c
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* @brief Implementation of a sleep functionality
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* @internal
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* @author ON Semiconductor
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* $Rev: 0.1 $
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* $Date: 02-05-2016 $
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******************************************************************************
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* Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
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* All rights reserved. This software and/or documentation is licensed by ON Semiconductor
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* under limited terms and conditions. The terms and conditions pertaining to the software
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* and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
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* (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
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* if applicable the software license agreement. Do not use this software and/or
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* documentation unless you have carefully read and you agree to the limited terms and
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* conditions. By using this software and/or documentation, you agree to the limited
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* terms and conditions.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
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* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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* @endinternal
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*
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* @ingroup spi_api
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*
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* @details
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* SPI implementation
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*
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*/
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#if DEVICE_SPI
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#include "spi.h"
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#include "PeripheralPins.h"
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#include "objects.h"
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#include "spi_api.h"
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#include "mbed_assert.h"
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#include "memory_map.h"
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#include "spi_ipc7207_map.h"
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#include "crossbar.h"
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#include "clock.h"
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#include "cmsis_nvic.h"
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#define SPI_FREQ_MAX 4000000
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void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
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{
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fSpiInit(obj, mosi, miso, sclk, ssel);
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}
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void spi_free(spi_t *obj)
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{
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fSpiClose(obj);
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}
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void spi_format(spi_t *obj, int bits, int mode, int slave)
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{
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/* Clear word width | Slave/Master | CPOL | CPHA | MSB first bits in control register */
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obj->membase->CONTROL.WORD &= ~(uint32_t)((True << SPI_WORD_WIDTH_BIT_POS) |
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(True << SPI_SLAVE_MASTER_BIT_POS) |
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(True << SPI_CPOL_BIT_POS) |
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(True << SPI_CPHA_BIT_POS));
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/* Configure word width | Slave/Master | CPOL | CPHA | MSB first bits in control register */
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obj->membase->CONTROL.WORD |= (uint32_t)(((bits >> 0x4) << SPI_WORD_WIDTH_BIT_POS) |
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(!slave << SPI_SLAVE_MASTER_BIT_POS) |
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((mode >> 0x1) << SPI_CPOL_BIT_POS) |
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((mode & 0x1) << SPI_CPHA_BIT_POS));
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}
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void spi_frequency(spi_t *obj, int hz)
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{
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/* If the frequency is outside the allowable range, set it to the max */
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if(hz > SPI_FREQ_MAX) {
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hz = SPI_FREQ_MAX;
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}
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obj->membase->FDIV = ((fClockGetPeriphClockfrequency() / hz) >> 1) - 1;
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}
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int spi_master_write(spi_t *obj, int value)
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{
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return(fSpiWriteB(obj, value));
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}
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int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
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char *rx_buffer, int rx_length, char write_fill) {
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int total = (tx_length > rx_length) ? tx_length : rx_length;
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for (int i = 0; i < total; i++) {
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char out = (i < tx_length) ? tx_buffer[i] : write_fill;
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char in = spi_master_write(obj, out);
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if (i < rx_length) {
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rx_buffer[i] = in;
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}
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}
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return total;
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}
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int spi_busy(spi_t *obj)
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{
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return(obj->membase->STATUS.BITS.XFER_IP);
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}
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uint8_t spi_get_module(spi_t *obj)
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{
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if(obj->membase == SPI1REG) {
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return 0; /* UART #1 */
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} else if(obj->membase == SPI2REG) {
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return 1; /* UART #2 */
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} else {
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return 2; /* Invalid address */
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}
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}
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int spi_slave_receive(spi_t *obj)
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{
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if(obj->membase->STATUS.BITS.RX_EMPTY != True){ /* if receive status is not empty */
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return True; /* Byte available to read */
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}
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return False; /* Byte not available to read */
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}
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int spi_slave_read(spi_t *obj)
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{
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int byte;
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while (obj->membase->STATUS.BITS.RX_EMPTY == True); /* Wait till Receive status is empty */
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byte = obj->membase->RX_DATA;
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return byte;
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}
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void spi_slave_write(spi_t *obj, int value)
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{
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while((obj->membase->STATUS.BITS.TX_FULL == True) && (obj->membase->STATUS.BITS.RX_FULL == True)); /* Wait till Tx/Rx status is full */
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obj->membase->TX_DATA = value;
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}
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#if DEVICE_SPI_ASYNCH /* TODO Not yet implemented */
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void spi_master_transfer(spi_t *obj, void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t handler, uint32_t event, DMAUsage hint)
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{
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uint32_t i;
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int ndata = 0;
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uint16_t *tx_ptr = (uint16_t *) tx;
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if(obj->spi->CONTROL.BITS.WORD_WIDTH == 0) {
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/* Word size 8 bits */
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WORD_WIDTH_MASK = 0xFF;
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} else if(obj->spi->CONTROL.BITS.WORD_WIDTH == 1) {
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/* Word size 16 bits */
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WORD_WIDTH_MASK = 0xFFFF;
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} else {
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/* Word size 32 bits */
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WORD_WIDTH_MASK = 0xFFFFFFFF;
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}
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//frame size
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if(tx_length == 0) {
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tx_length = rx_length;
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tx = (void*) 0;
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}
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//set tx rx buffer
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obj->tx_buff.buffer = (void *)tx;
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obj->rx_buff.buffer = rx;
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obj->tx_buff.length = tx_length;
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obj->rx_buff.length = rx_length;
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obj->tx_buff.pos = 0;
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obj->rx_buff.pos = 0;
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obj->tx_buff.width = bit_width;
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obj->rx_buff.width = bit_width;
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if((obj->spi.bits == 9) && (tx != 0)) {
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// Make sure we don't have inadvertent non-zero bits outside 9-bit frames which could trigger unwanted operation
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for(i = 0; i < (tx_length / 2); i++) {
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tx_ptr[i] &= 0x1FF;
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}
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}
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// enable events
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obj->spi.event |= event;
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// set sleep_level
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enable irq
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//write async
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if ( && ) {
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}
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while ((obj->tx_buff.pos < obj->tx_buff.length) &&
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(obj->spi->STATUS.BITS.TX_FULL == False) &&
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(obj->spi->STATUS.BITS.RX_FULL == False)) {
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// spi_buffer_tx_write(obj);
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if (obj->tx_buff.buffer == (void *)0) {
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data = SPI_FILL_WORD;
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} else {
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uint16_t *tx = (uint16_t *)(obj->tx_buff.buffer);
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data = tx[obj->tx_buff.pos] & 0xFF;
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}
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obj->spi->TX_DATA = data;
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}
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ndata++;
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}
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return ndata;
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}
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uint32_t spi_irq_handler_asynch(spi_t *obj)
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{
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}
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uint8_t spi_active(spi_t *obj)
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{
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}
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void spi_abort_asynch(spi_t *obj)
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{
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}
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#endif /* DEVICE_SPI_ASYNCH */
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#endif /* DEVICE_SPI */ |