mirror of https://github.com/ARMmbed/mbed-os.git
291 lines
11 KiB
C
291 lines
11 KiB
C
/**
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******************************************************************************
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* @file memory_map.h
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* @brief Defines the silicon memory map. All peripheral devices shall be mapped in structures.
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* @internal
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* @author ON Semiconductor
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* $Rev: 3525 $
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* $Date: 2015-07-20 15:24:25 +0530 (Mon, 20 Jul 2015) $
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******************************************************************************
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* Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
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* All rights reserved. This software and/or documentation is licensed by ON Semiconductor
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* under limited terms and conditions. The terms and conditions pertaining to the software
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* and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
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* (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
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* if applicable the software license agreement. Do not use this software and/or
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* documentation unless you have carefully read and you agree to the limited terms and
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* conditions. By using this software and/or documentation, you agree to the limited
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* terms and conditions.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
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* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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* @endinternal
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*
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* @ingroup bsp
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@verbatim
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+-----------------+
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| | ,_________________________
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| Private Per. | |PMUREG 0x4001D000|
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0xE0000000 +-----------------+ |PADREG 0x4001C000|
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| |_____________|CLOCKREG 0x4001B000|
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| PERIPHERALS | |RFANAREG 0x40019000|
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+-----------------+ |RESETREG 0x40018000|
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| | |FLASHREG 0x40017000|
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0x3FFF8000 |SRAM A 32K | |AESREG 0x40016000|
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+-----------------+ |ADCREG 0x40015000|
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| | |MACHWREG 0x40014000|
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|SRAM B 16K | |RANDREG 0x40011000|
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0x3FFF4000 +-----------------+ |CROSSBREG 0x40010000|
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| | |RTCREG 0x4000F000|
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0x24000100 |SRAM DMA 7B | |GPIOREG 0x4000C000|
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+-----------------+ |PWMREG 0x4000B000|
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0x24000000 |SRAM MAC 256B | |WDTREG 0x4000A000|
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+-----------------+ |UARTREG 0x40008000|
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| 320K | |I2CREG 0x40007000|
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0x00102000 |FLASHB | |SPIREG 0x40006000|
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0x00100000 |FLASHB Inf Block | |UARTREG 0x40005000|
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+-----------------+ |TIM2REG 0x40002000|
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| 320K | |TIM1REG 0x40001000|
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0x00002000 |FLASHA | |TIM0REG 0x40000000|
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0x00000000 |FLASHA Inf Block | '`''''''''''''''''''''''''
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'`'''''''''''''''''
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@endverbatim
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*/
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#ifndef _MEMORY_MAP_H_
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#define _MEMORY_MAP_H_
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/*************************************************************************************************
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* *
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* Header files *
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* *
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*************************************************************************************************/
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#include <stdint.h>
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#include "architecture.h"
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// Register maps of HW modules controlled with device drivers
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#include "adc_sar_map.h"
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#include "aes_map.h"
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#include "flash_map.h"
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#include "gpio_map.h"
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#include "i2c_ipc7208_map.h"
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#include "pwm_map.h"
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#include "rtc_map.h"
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#include "spi_ipc7207_map.h"
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#include "timer_map.h"
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#include "uart_16c550_map.h"
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#include "wdt_map.h"
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// Register maps of HW modules controlled with specific functions
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#include "clock_map.h"
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#include "crossbar_map.h"
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#include "dma_map.h"
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#include "macHw_map.h"
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#include "pad_map.h"
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#include "pmu_map.h"
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#include "random_map.h"
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#include "reset_map.h"
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#include "rfAna_map.h"
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#include "test_map.h"
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// Trim structure map
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#include "trim_map.h"
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/*************************************************************************************************
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* *
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* Symbolic Constants *
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* *
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*************************************************************************************************/
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/** Trim structure mapping
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*
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*/
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#define TRIMREG_BASE ((uint32_t)0x1FA0)
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#define TRIMREG ((TrimReg_t *)TRIMREG_BASE)
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/** User trim structure mapping
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*
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*/
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#define USRETRIMREG_BASE ((uint32_t)0x2800)
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#define USERTRIMREG ((UserTrimReg_t *)USRETRIMREG_BASE)
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/** DMA HW Registers Offset */
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#define DMAREG_BASE ((uint32_t)0x24000400)
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/** DMA HW Structure Overlay */
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#define DMAREG ((DmaReg_pt)DMAREG_BASE)
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/** MAC MATCH HW Registers Offset */
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#define MACMATCHREG_BASE ((uint32_t)0x24000100)
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/** MAC MATCH HW Structure Overlay */
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#define MACMATCHREG ((volatile uint8_t *)MACMATCHREG_BASE)
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/** MAC RX HW Registers Offset */
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#define MACRXREG_BASE ((uint32_t)0x24000080)
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/** MAC RX HW Structure Overlay */
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#define MACRXREG ((volatile uint8_t *)MACRXREG_BASE)
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/** MAC TX HW Registers Offset */
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#define MACTXREG_BASE ((uint32_t)0x24000000)
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/** MAC TX HW Structure Overlay */
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#define MACTXREG ((volatile uint8_t *)MACTXREG_BASE)
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/** TEST Interface for flash HW Registers Offset */
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#define TESTNVMREG_BASE ((uint32_t)0x4001F140)
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/** TEST Interface for flash HW Structure Overlay */
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#define TESTNVMREG ((TestNvmReg_pt)TESTNVMREG_BASE)
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/** Test Interface for digital HW Registers Offset */
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#define TESTDIGREG_BASE ((uint32_t)0x4001F100)
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/** Test Interface for digital HW Structure Overlay */
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#define TESTDIGREG ((TestDigReg_pt)TESTDIGREG_BASE)
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/** Test Interface HW Registers Offset */
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#define TESTREG_BASE ((uint32_t)0x4001F000)
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/** Test Interface HW Structure Overlay */
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#define TESTREG ((TestReg_pt)TESTREG_BASE)
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/** Device option HW Registers Offset */
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#define DEVOPTREG_BASE ((uint32_t)0x4001E000)
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/** MAC TX HW Structure Overlay */
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#define DEVOPTREG ((volatile uint32_t *)DEVOPTREG_BASE)
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/** PMU HW Registers Offset */
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#define PMUREG_BASE ((uint32_t)0x4001D000)
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/** PMU HW Structure Overlay */
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#define PMUREG ((PmuReg_pt)PMUREG_BASE)
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/** PAD Control HW Registers Offset */
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#define PADREG_BASE ((uint32_t)0x4001C000)
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/** PAD Control HW Structure Overlay */
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#define PADREG ((PadReg_pt)PADREG_BASE)
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/** Clock Control HW Registers Offset */
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#define CLOCKREG_BASE ((uint32_t)0x4001B000)
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/** Clock Control HW Structure Overlay */
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#define CLOCKREG ((ClockReg_pt)CLOCKREG_BASE)
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/** Analogue Trim HW Registers Offset */
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#define RFANATRIMREG_BASE ((uint32_t)0x40019080)
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/** Analogue Trim HW Structure Overlay */
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#define RFANATRIMREG ((RfAnaTrimReg_pt)RFANATRIMREG_BASE)
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/** Analogue RF HW Registers Offset */
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#define RFANAREG_BASE ((uint32_t)0x40019000)
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/** Analogue RF HW Structure Overlay */
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#define RFANAREG ((RfAnaReg_pt)RFANAREG_BASE)
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/** Reset Cause HW Registers Offset */
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#define RESETREG_BASE ((uint32_t)0x40018000)
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/** Reset Cause HW Structure Overlay */
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#define RESETREG ((ResetReg_pt)RESETREG_BASE)
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/** FLASH Control HW Registers Offset */
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#define FLASHREG_BASE ((uint32_t)0x40017000)
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/** FLASH Control HW Structure Overlay */
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#define FLASHREG ((FlashReg_pt)FLASHREG_BASE)
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/** AES Encryption HW Registers Offset */
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#define AESREG_BASE ((uint32_t)0x40016000)
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/** AES Encryption HW Structure Overlay */
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#define AESREG ((AesReg_pt)AESREG_BASE)
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/** SAR ADC HW Registers Offset */
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#define ADCREG_BASE ((uint32_t)0x40015000)
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/** SAR ADC HW Structure Overlay */
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#define ADCREG ((AdcReg_pt)ADCREG_BASE)
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/** Demodulator HW Registers Offset */
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#define DMDREG_BASE ((uint32_t)0x40014100)
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/** Demodulator HW Structure Overlay */
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#define DMDREG ((DmdReg_pt)DMDREG_BASE)
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/** MAC Control HW Registers Offset */
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#define MACHWREG_BASE ((uint32_t)0x40014000)
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/** MAC Control HW Structure Overlay */
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#define MACHWREG ((MacHwReg_pt)MACHWREG_BASE)
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/** Random Generator HW Registers Offset */
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#define RANDREG_BASE ((uint32_t)0x40011000)
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/** Random Generator HW Structure Overlay */
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#define RANDREG ((RandReg_pt)RANDREG_BASE)
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/** Cross Bar HW Registers Offset */
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#define CROSSBREG_BASE ((uint32_t)0x40010000)
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/** Cross Bar HW Structure Overlay */
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#define CROSSBREG ((CrossbReg_pt)CROSSBREG_BASE)
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/** Real Time Clock HW Registers Offset */
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#define RTCREG_BASE ((uint32_t)0x4000F000)
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/** Real Time Clock HW Structure Overlay */
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#define RTCREG ((RtcReg_pt)RTCREG_BASE)
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/** GPIO HW Registers Offset */
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#define GPIOREG_BASE ((uint32_t)0x4000C000)
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/** GPIO HW Structure Overlay */
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#define GPIOREG ((GpioReg_pt)GPIOREG_BASE)
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/** PWM HW Registers Offset */
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#define PWMREG_BASE ((uint32_t)0x4000B000)
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/** PWM HW Structure Overlay */
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#define PWMREG ((PwmReg_pt)PWMREG_BASE)
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/** Watchdog Timer HW Registers Offset */
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#define WDTREG_BASE ((uint32_t)0x4000A000)
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/** Watchdog Timer HW Structure Overlay */
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#define WDTREG ((WdtReg_pt)WDTREG_BASE)
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/** UART 2 HW Registers Offset */
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#define UART2REG_BASE ((uint32_t)0x40008000)
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/** UART 2 HW Structure Overlay */
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#define UART2REG ((Uart16C550Reg_pt)UART2REG_BASE)
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/** I2C HW Registers Offset */
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#define I2C1REG_BASE ((uint32_t)0x40007000)
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/** I2C HW Structure Overlay */
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#define I2C1REG ((I2cIpc7208Reg_pt)I2C1REG_BASE)
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/** SPI HW Registers Offset */
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#define SPI1REG_BASE ((uint32_t)0x40006000)
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/** SPI HW Structure Overlay */
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#define SPI1REG ((SpiIpc7207Reg_pt)SPI1REG_BASE)
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/** UART1 HW Registers Offset */
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#define UART1REG_BASE ((uint32_t)0x40005000)
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/** UART1 HW Structure Overlay */
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#define UART1REG ((Uart16C550Reg_pt)UART1REG_BASE)
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#define UARTREG_BASES { UART1REG_BASE, UART2REG_BASE}
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/** Timer 2 HW Registers Offset */
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#define TIM2REG_BASE ((uint32_t)0x40002000)
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/** Timer 2 HW Structure Overlay */
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#define TIM2REG ((TimerReg_pt)TIM2REG_BASE)
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/** Timer 1 HW Registers Offset */
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#define TIM1REG_BASE ((uint32_t)0x40001000)
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/** Timer 1 HW Structure Overlay */
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#define TIM1REG ((TimerReg_pt)TIM1REG_BASE)
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/** Timer 0 HW Registers Offset */
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#define TIM0REG_BASE ((uint32_t)0x40000000)
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/** Timer 0 HW Structure Overlay */
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#define TIM0REG ((TimerReg_pt)TIM0REG_BASE)
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/** I2C2 HW Registers Offset */
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#define I2C2REG_BASE ((uint32_t)0x4000D000)
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/** I2C2 HW Structure Overlay */
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#define I2C2REG ((I2cIpc7208Reg_pt)I2C2REG_BASE)
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/** SPI2 HW Registers Offset */
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#define SPI2REG_BASE ((uint32_t)0x40009000)
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/** SPI2 HW Structure Overlay */
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#define SPI2REG ((SpiIpc7207Reg_pt)SPI2REG_BASE)
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#endif /*_MEMORY_MAP_H_*/
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