mirror of https://github.com/ARMmbed/mbed-os.git
699 lines
26 KiB
C
699 lines
26 KiB
C
/*!
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* \file STM32WL_radio_driver.h
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* Copyright 2021 STMicroelectronics
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* \brief STM32WL driver implementation
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*
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*/
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#ifndef MBED_LORA_RADIO_DRV_STM32WL_RADIO_DRIVER_H_
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#define MBED_LORA_RADIO_DRV_STM32WL_RADIO_DRIVER_H_
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#include "LoRaRadio.h"
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#define RFO_LP 1
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#define RFO_HP 2
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/* STM32WL Nucleo antenna switch defines */
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#define RBI_CONF_RFO_LP_HP 0
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#define RBI_CONF_RFO_LP 1
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#define RBI_CONF_RFO_HP 2
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typedef enum {
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RBI_SWITCH_OFF = 0,
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RBI_SWITCH_RX = 1,
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RBI_SWITCH_RFO_LP = 2,
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RBI_SWITCH_RFO_HP = 3,
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} RBI_Switch_TypeDef;
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/**
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* Indicates whether or not TCXO is supported by the board
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* 0: TCXO not supported
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* 1: TCXO supported
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*/
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#define IS_TCXO_SUPPORTED 1U
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/**
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* @brief drive value used anytime radio is NOT in TX low power mode
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*/
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#define SMPS_DRIVE_SETTING_DEFAULT SMPS_DRV_40
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/**
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* @brief drive value used anytime radio is in TX low power mode
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* TX low power mode is the worst case because the PA sinks from SMPS
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* while in high power mode, current is sunk directly from the battery
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*/
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#define SMPS_DRIVE_SETTING_MAX SMPS_DRV_60
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/*!
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* \brief Change the value on the device internal trimming capacitor
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*/
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#define REG_XTA_TRIM 0x0911
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/*!
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* \brief Change the value on the device internal trimming capacitor
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*/
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#define REG_XTB_TRIM 0x0912
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/*!
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* \brief Set the current max value in the over current protection
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*/
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#define REG_OCP 0x08E7
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/*!
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* \brief PA Clamping threshold
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*/
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#define REG_TX_CLAMP 0x08D8
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/**
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* @brief Sub-GHz radio register (re) definition
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* @note The sub-GHz radio peripheral registers can be accessed by sub-GHz radio command
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* SUBGRF_WriteRegisters() and SUBGRF_ReadRegisters() "
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*/
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/*Sub-GHz radio generic bit synchronization register*/
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#define SUBGHZ_GBSYNCR REG_BIT_SYNC
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/*Sub-GHz radio generic packet control 1A register*/
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#define SUBGHZ_GPKTCTL1AR REG_LR_WHITSEEDBASEADDR_MSB
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/*Sub-GHz radio generic whitening LSB register*/
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#define SUBGHZ_GWHITEINIRL REG_LR_WHITSEEDBASEADDR_LSB
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/*Sub-GHz radio generic CRC initial MSB register*/
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#define SUBGHZ_GCRCINIRH REG_LR_CRCSEEDBASEADDR
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/*Sub-GHz radio generic CRC initial LSB register*/
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#define SUBGHZ_GCRCINIRL 0x06BD
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/*Sub-GHz radio generic CRC polynomial MSB register*/
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#define SUBGHZ_GCRCPOLRH REG_LR_CRCPOLYBASEADDR
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/*Sub-GHz radio generic CRC polynomial LSB register*/
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#define SUBGHZ_GCRCPOLRL 0x06BF
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/*Sub-GHz radio generic synchronization word control register 7*/
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#define SUBGHZ_GSYNCR7 REG_LR_SYNCWORDBASEADDRESS
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/*Sub-GHz radio generic synchronization word control register 6*/
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#define SUBGHZ_GSYNCR6 0x06C1
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/*Sub-GHz radio generic synchronization word control register 5*/
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#define SUBGHZ_GSYNCR5 0x06C2
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/*Sub-GHz radio generic synchronization word control register 4*/
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#define SUBGHZ_GSYNCR4 0x06C3
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/*Sub-GHz radio generic synchronization word control register 3*/
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#define SUBGHZ_GSYNCR3 0x06C4
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/*Sub-GHz radio generic synchronization word control register 2*/
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#define SUBGHZ_GSYNCR2 0x06C5
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/*Sub-GHz radio generic synchronization word control register 1*/
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#define SUBGHZ_GSYNCR1 0x06C6
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/*Sub-GHz radio generic synchronization word control register 0*/
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#define SUBGHZ_GSYNCR0 0x06C7
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/*Sub-GHz radio LoRa synchronization word MSB register*/
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#define SUBGHZ_LSYNCRH REG_LR_SYNCWORD
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/*Sub-GHz radio LoRa synchronization word LSB register*/
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#define SUBGHZ_LSYNCRL 0x0741
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/*Sub-GHz radio random number register 3*/
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#define SUBGHZ_RNGR3 RANDOM_NUMBER_GENERATORBASEADDR
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/*Sub-GHz radio random number register 2*/
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#define SUBGHZ_RNGR2 0x081A
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/*Sub-GHz radio random number register 1*/
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#define SUBGHZ_RNGR1 0x081B
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/*Sub-GHz radio random number register 0*/
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#define SUBGHZ_RNGR0 0x081C
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/*Sub-GHz radio receiver gain control register*/
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#define SUBGHZ_RXGAINCR REG_RX_GAIN
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/*Sub-GHz radio PA over current protection register*/
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#define SUBGHZ_PAOCPR REG_OCP
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/*Sub-GHz radio HSE32 OSC_IN capacitor trim register*/
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#define SUBGHZ_HSEINTRIMR REG_XTA_TRIM
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/*Sub-GHz radio HSE32 OSC_OUT capacitor trim register*/
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#define SUBGHZ_HSEOUTTRIMR REG_XTB_TRIM
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/*Sub-GHz radio SMPS control 0 register */
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#define SUBGHZ_SMPSC0R 0x0916
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/*Sub-GHz radio power control register*/
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#define SUBGHZ_PCR 0x091A
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/*Sub-GHz radio SMPS control 2 register */
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#define SUBGHZ_SMPSC2R 0x0923
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#define SMPS_CLK_DET_ENABLE ((uint8_t) (1<<6))
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#define SMPS_DRV_20 ((uint8_t) ((0x0)<<1))
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#define SMPS_DRV_40 ((uint8_t) ((0x1)<<1))
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#define SMPS_DRV_60 ((uint8_t) ((0x2)<<1))
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#define SMPS_DRV_100 ((uint8_t) ((0x3)<<1))
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#define SMPS_DRV_MASK ((uint8_t) ((0x3)<<1))
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/*!
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* \brief Provides the frequency of the chip running on the radio and the frequency step
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*
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* \remark These defines are used for computing the frequency divider to set the RF frequency
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*/
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#define XTAL_FREQ 32000000
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#define FREQ_DIV 33554432
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#define FREQ_STEP 0.95367431640625 // ((double)(XTAL_FREQ / (double)FREQ_DIV))
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#define FREQ_ERR 0.47683715820312
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/*!
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* \brief List of matching supported by the STM32WL SubGHz
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*/
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#define MATCHING_FREQ_915 0
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#define MATCHING_FREQ_780 1
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#define MATCHING_FREQ_490 2
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#define MATCHING_FREQ_434 3
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#define MATCHING_FREQ_280 4
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#define MATCHING_FREQ_169 5
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#define MATCHING_FREQ_868 6
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/*!
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* \brief Compensation delay for SetAutoTx/Rx functions in 15.625 microseconds
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*/
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#define AUTO_RX_TX_OFFSET 2
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/*!
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* \brief LFSR initial value to compute IBM type CRC
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*/
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#define CRC_IBM_SEED 0xFFFF
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/*!
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* \brief LFSR initial value to compute CCIT type CRC
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*/
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#define CRC_CCITT_SEED 0x1D0F
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/*!
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* \brief Polynomial used to compute IBM CRC
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*/
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#define CRC_POLYNOMIAL_IBM 0x8005
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/*!
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* \brief Polynomial used to compute CCIT CRC
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*/
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#define CRC_POLYNOMIAL_CCITT 0x1021
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/*!
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* \brief The address of the register holding the first byte defining the CRC seed
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*
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*/
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#define REG_LR_CRCSEEDBASEADDR 0x06BC
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/*!
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* \brief The address of the register holding the first byte defining the CRC polynomial
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*/
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#define REG_LR_CRCPOLYBASEADDR 0x06BE
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/*!
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* \brief The address of the register holding the first byte defining the whitening seed
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*/
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#define REG_LR_WHITSEEDBASEADDR_MSB 0x06B8
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#define REG_LR_WHITSEEDBASEADDR_LSB 0x06B9
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/*!
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* \brief The address of the register holding the packet configuration
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*/
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#define REG_LR_PACKETPARAMS 0x0704
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/*!
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* \brief The address of the register holding the payload size
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*/
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#define REG_LR_PAYLOADLENGTH 0x0702
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/*!
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* \brief The addresses of the registers holding SyncWords values
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*/
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#define REG_LR_SYNCWORDBASEADDRESS 0x06C0
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/*!
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* \brief The addresses of the register holding LoRa Modem SyncWord value
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*/
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#define REG_LR_SYNCWORD 0x0740
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/*!
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* Syncword for Private LoRa networks
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*/
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#define LORA_MAC_PRIVATE_SYNCWORD 0x1424
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/*!
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* Syncword for Public LoRa networks
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*/
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#define LORA_MAC_PUBLIC_SYNCWORD 0x3444
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/*!
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* The address of the register giving a 4 bytes random number
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*/
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#define RANDOM_NUMBER_GENERATORBASEADDR 0x0819
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/*!
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* The address of the register holding RX Gain value (0x94: power saving, 0x96: rx boosted)
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*/
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#define REG_RX_GAIN 0x08AC
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/*!
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* The address of the register holding frequency error indication
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*/
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#define REG_FREQUENCY_ERRORBASEADDR 0x076B
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/*!
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* Change the value on the device internal trimming capacitor
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*/
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#define REG_XTA_TRIM 0x0911
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/*!
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* Set the current max value in the over current protection
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*/
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#define REG_OCP 0x08E7
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/*!
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* \brief Represents the Rx internal counters values when GFSK or LoRa packet type is used
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*/
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typedef struct {
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radio_modems_t modem_type; //!< Packet to which the packet status are referring to.
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uint16_t packet_received;
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uint16_t crc_ok;
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uint16_t length_error;
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} rx_counter_t;
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/*!
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* \brief Represents a calibration configuration
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*/
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typedef union {
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struct {
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uint8_t rc64k_enable : 1; //!< Calibrate RC64K clock
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uint8_t rc13m_enable : 1; //!< Calibrate RC13M clock
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uint8_t pll_enable : 1; //!< Calibrate PLL
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uint8_t adc_pulse_enable : 1; //!< Calibrate ADC Pulse
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uint8_t adc_bulkN_enable : 1; //!< Calibrate ADC bulkN
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uint8_t adc_bulkP_enable : 1; //!< Calibrate ADC bulkP
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uint8_t img_enable : 1;
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uint8_t pad : 1;
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} fields;
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uint8_t value;
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} calibration_params_t;
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/*!
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* \brief Represents the possible radio system error states
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*/
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typedef union {
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struct {
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uint8_t rc64k_calib : 1; //!< RC 64kHz oscillator calibration failed
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uint8_t rc13m_calib : 1; //!< RC 13MHz oscillator calibration failed
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uint8_t pll_calib : 1; //!< PLL calibration failed
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uint8_t adc_calib : 1; //!< ADC calibration failed
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uint8_t img_calib : 1; //!< Image calibration failed
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uint8_t xosc_start : 1; //!< XOSC oscillator failed to start
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uint8_t pll_lock : 1; //!< PLL lock failed
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uint8_t buck_start : 1; //!< Buck converter failed to start
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uint8_t pa_ramp : 1; //!< PA ramp failed
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uint8_t reserved : 7; //!< reserved
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} fields;
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uint16_t value;
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} radio_error_t;
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/*!
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* \brief Represents the operating mode the radio is actually running
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*/
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typedef enum {
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MODE_SLEEP = 0x00, //! The radio is in sleep mode
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MODE_DEEP_SLEEP, //! The radio is in deep-sleep mode
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MODE_STDBY_RC, //! The radio is in standby mode with RC oscillator
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MODE_STDBY_XOSC, //! The radio is in standby mode with XOSC oscillator
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MODE_FS, //! The radio is in frequency synthesis mode
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MODE_TX, //! The radio is in transmit mode
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MODE_RX, //! The radio is in receive mode
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MODE_RX_DC, //! The radio is in receive duty cycle mode
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MODE_CAD //! The radio is in channel activity detection mode
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} radio_operating_mode_t;
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/*!
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* \brief Declares the oscillator in use while in standby mode
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*
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* Using the STDBY_RC standby mode allow to reduce the energy consumption
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* STDBY_XOSC should be used for time critical applications
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*/
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typedef enum {
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STDBY_RC = 0x00,
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STDBY_XOSC = 0x01,
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} radio_standby_mode_t;
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/*!
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* \brief Declares the power regulation used to power the device
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*
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* This command allows the user to specify if DC-DC or LDO is used for power regulation.
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* Using only LDO implies that the Rx or Tx current is doubled
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*/
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typedef enum {
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USE_LDO = 0x00, // default
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USE_DCDC = 0x01,
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} radio_regulator_mode_t;
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/*!
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* \brief Represents the ramping time for power amplifier
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*/
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typedef enum {
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RADIO_RAMP_10_US = 0x00,
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RADIO_RAMP_20_US = 0x01,
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RADIO_RAMP_40_US = 0x02,
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RADIO_RAMP_80_US = 0x03,
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RADIO_RAMP_200_US = 0x04,
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RADIO_RAMP_800_US = 0x05,
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RADIO_RAMP_1700_US = 0x06,
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RADIO_RAMP_3400_US = 0x07,
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} radio_ramp_time_t;
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/*!
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* \brief Represents the number of symbols to be used for channel activity detection operation
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*/
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typedef enum {
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LORA_CAD_01_SYMBOL = 0x00,
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LORA_CAD_02_SYMBOL = 0x01,
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LORA_CAD_04_SYMBOL = 0x02,
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LORA_CAD_08_SYMBOL = 0x03,
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LORA_CAD_16_SYMBOL = 0x04,
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} lora_cad_symbols_t;
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/*!
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* \brief Represents the Channel Activity Detection actions after the CAD operation is finished
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*/
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typedef enum {
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LORA_CAD_ONLY = 0x00,
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LORA_CAD_RX = 0x01,
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LORA_CAD_LBT = 0x10,
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} cad_exit_modes_t;
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/*!
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* \brief Represents the modulation shaping parameter
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*/
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typedef enum {
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MOD_SHAPING_OFF = 0x00,
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MOD_SHAPING_G_BT_03 = 0x08,
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MOD_SHAPING_G_BT_05 = 0x09,
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MOD_SHAPING_G_BT_07 = 0x0A,
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MOD_SHAPING_G_BT_1 = 0x0B,
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} radio_mod_shaping_t;
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/*!
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* \brief Represents the modulation shaping parameter
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*/
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typedef enum {
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RX_BW_4800 = 0x1F,
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RX_BW_5800 = 0x17,
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RX_BW_7300 = 0x0F,
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RX_BW_9700 = 0x1E,
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RX_BW_11700 = 0x16,
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RX_BW_14600 = 0x0E,
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RX_BW_19500 = 0x1D,
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RX_BW_23400 = 0x15,
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RX_BW_29300 = 0x0D,
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RX_BW_39000 = 0x1C,
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RX_BW_46900 = 0x14,
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RX_BW_58600 = 0x0C,
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RX_BW_78200 = 0x1B,
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RX_BW_93800 = 0x13,
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RX_BW_117300 = 0x0B,
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RX_BW_156200 = 0x1A,
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RX_BW_187200 = 0x12,
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RX_BW_234300 = 0x0A,
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RX_BW_312000 = 0x19,
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RX_BW_373600 = 0x11,
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RX_BW_467000 = 0x09,
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} radio_rx_bandwidth_t;
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/*!
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* \brief Represents the possible spreading factor values in LoRa packet types
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*/
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typedef enum {
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LORA_SF5 = 0x05,
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LORA_SF6 = 0x06,
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LORA_SF7 = 0x07,
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LORA_SF8 = 0x08,
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LORA_SF9 = 0x09,
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LORA_SF10 = 0x0A,
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LORA_SF11 = 0x0B,
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LORA_SF12 = 0x0C,
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} lora_spread_factors_t;
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/*!
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* \brief Represents the bandwidth values for LoRa packet type
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*/
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typedef enum {
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LORA_BW_500 = 6,
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LORA_BW_250 = 5,
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LORA_BW_125 = 4,
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LORA_BW_062 = 3,
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LORA_BW_041 = 10,
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LORA_BW_031 = 2,
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LORA_BW_020 = 9,
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LORA_BW_015 = 1,
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LORA_BW_010 = 8,
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LORA_BW_007 = 0,
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} lora_bandwidths_t;
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const uint8_t lora_bandwidths [] = {LORA_BW_125, LORA_BW_250, LORA_BW_500};
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/*!
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* \brief Represents the coding rate values for LoRa packet type
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*/
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typedef enum {
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LORA_CR_4_5 = 0x01,
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LORA_CR_4_6 = 0x02,
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LORA_CR_4_7 = 0x03,
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LORA_CR_4_8 = 0x04,
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} lora_coding_states_t;
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/*!
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* \brief Represents the preamble length used to detect the packet on Rx side
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*/
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typedef enum {
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RADIO_PREAMBLE_DETECTOR_OFF = 0x00, //!< Preamble detection length off
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RADIO_PREAMBLE_DETECTOR_08_BITS = 0x04, //!< Preamble detection length 8 bits
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RADIO_PREAMBLE_DETECTOR_16_BITS = 0x05, //!< Preamble detection length 16 bits
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RADIO_PREAMBLE_DETECTOR_24_BITS = 0x06, //!< Preamble detection length 24 bits
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RADIO_PREAMBLE_DETECTOR_32_BITS = 0x07, //!< Preamble detection length 32 bit
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} radio_preamble_detection_t;
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/*!
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* \brief Represents the possible combinations of SyncWord correlators activated
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*/
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typedef enum {
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RADIO_ADDRESSCOMP_FILT_OFF = 0x00, //!< No correlator turned on, i.e. do not search for SyncWord
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RADIO_ADDRESSCOMP_FILT_NODE = 0x01,
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RADIO_ADDRESSCOMP_FILT_NODE_BROAD = 0x02,
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} radio_address_filter_t;
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/*!
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* \brief Radio packet length mode
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*/
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typedef enum {
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RADIO_PACKET_VARIABLE_LENGTH = 0x00, //!< The packet is on variable size, header included
|
|
RADIO_PACKET_FIXED_LENGTH = 0x01, //!< The packet is known on both sides, no header included in the packet
|
|
} radio_pkt_length_t;
|
|
|
|
/*!
|
|
* \brief Represents the CRC length
|
|
*/
|
|
typedef enum radio_crc_types_e {
|
|
RADIO_CRC_OFF = 0x01, //!< No CRC in use
|
|
RADIO_CRC_1_BYTES = 0x00,
|
|
RADIO_CRC_2_BYTES = 0x02,
|
|
RADIO_CRC_1_BYTES_INV = 0x04,
|
|
RADIO_CRC_2_BYTES_INV = 0x06,
|
|
RADIO_CRC_2_BYTES_IBM = 0xF1,
|
|
RADIO_CRC_2_BYTES_CCIT = 0xF2,
|
|
} radio_crc_types_t;
|
|
|
|
/*!
|
|
* \brief Radio whitening mode activated or deactivated
|
|
*/
|
|
typedef enum {
|
|
RADIO_DC_FREE_OFF = 0x00,
|
|
RADIO_DC_FREEWHITENING = 0x01,
|
|
} radio_whitening_mode_t;
|
|
|
|
/*!
|
|
* \brief Holds the lengths mode of a LoRa packet type
|
|
*/
|
|
typedef enum {
|
|
LORA_PACKET_VARIABLE_LENGTH = 0x00, //!< The packet is on variable size, header included
|
|
LORA_PACKET_FIXED_LENGTH = 0x01, //!< The packet is known on both sides, no header included in the packet
|
|
LORA_PACKET_EXPLICIT = LORA_PACKET_VARIABLE_LENGTH,
|
|
LORA_PACKET_IMPLICIT = LORA_PACKET_FIXED_LENGTH,
|
|
} lora_pkt_length_t;
|
|
|
|
/*!
|
|
* \brief Represents the CRC mode for LoRa packet type
|
|
*/
|
|
typedef enum {
|
|
LORA_CRC_ON = 0x01, //!< CRC activated
|
|
LORA_CRC_OFF = 0x00, //!< CRC not used
|
|
} lora_crc_mode_t;
|
|
|
|
/*!
|
|
* \brief Represents the IQ mode for LoRa packet type
|
|
*/
|
|
typedef enum {
|
|
LORA_IQ_NORMAL = 0x00,
|
|
LORA_IQ_INVERTED = 0x01,
|
|
} lora_IQ_mode_t;
|
|
|
|
/*!
|
|
* \brief Represents the volatge used to control the TCXO on/off from DIO3
|
|
*/
|
|
typedef enum {
|
|
TCXO_CTRL_1_6V = 0x00,
|
|
TCXO_CTRL_1_7V = 0x01,
|
|
TCXO_CTRL_1_8V = 0x02,
|
|
TCXO_CTRL_2_2V = 0x03,
|
|
TCXO_CTRL_2_4V = 0x04,
|
|
TCXO_CTRL_2_7V = 0x05,
|
|
TCXO_CTRL_3_0V = 0x06,
|
|
TCXO_CTRL_3_3V = 0x07,
|
|
} radio_TCXO_ctrl_voltage_t;
|
|
|
|
/*!
|
|
* \brief Represents the interruption masks available for the radio
|
|
*
|
|
* \remark Note that not all these interruptions are available for all packet types
|
|
*/
|
|
typedef enum {
|
|
IRQ_RADIO_NONE = 0x0000,
|
|
IRQ_TX_DONE = 0x0001,
|
|
IRQ_RX_DONE = 0x0002,
|
|
IRQ_PREAMBLE_DETECTED = 0x0004,
|
|
IRQ_SYNCWORD_VALID = 0x0008,
|
|
IRQ_HEADER_VALID = 0x0010,
|
|
IRQ_HEADER_ERROR = 0x0020,
|
|
IRQ_CRC_ERROR = 0x0040,
|
|
IRQ_CAD_DONE = 0x0080,
|
|
IRQ_CAD_ACTIVITY_DETECTED = 0x0100,
|
|
IRQ_RX_TX_TIMEOUT = 0x0200,
|
|
IRQ_RADIO_ALL = 0xFFFF,
|
|
} radio_irq_masks_t;
|
|
|
|
|
|
/*!
|
|
* \brief Structure describing the radio status
|
|
*/
|
|
typedef union {
|
|
uint8_t value;
|
|
struct {
|
|
//bit order is lsb -> msb
|
|
uint8_t reserved : 1; //!< Reserved
|
|
uint8_t cmd_status : 3; //!< Command status
|
|
uint8_t chip_mode : 3; //!< Chip mode
|
|
uint8_t cpu_busy : 1; //!< Flag for CPU radio busy
|
|
} fields;
|
|
} radio_status_t;
|
|
|
|
/*!
|
|
* \brief Structure describing the error codes for callback functions
|
|
*/
|
|
typedef enum {
|
|
IRQ_HEADER_ERROR_CODE = 0x01,
|
|
IRQ_SYNCWORD_ERROR_CODE = 0x02,
|
|
IRQ_CRC_ERROR_CODE = 0x04,
|
|
} irq_error_t;
|
|
|
|
|
|
typedef enum {
|
|
IRQ_PBL_DETECT_CODE = 0x01,
|
|
IRQ_SYNCWORD_VALID_CODE = 0x02,
|
|
IRQ_HEADER_VALID_CODE = 0x04,
|
|
} irq_valid_codes_t;
|
|
|
|
typedef enum {
|
|
IRQ_RX_TIMEOUT = 0x00,
|
|
IRQ_TX_TIMEOUT = 0x01,
|
|
} irq_timeout_t;
|
|
|
|
typedef enum {
|
|
RECEPTION_MODE_SINGLE = 0,
|
|
RECEPTION_MODE_CONTINUOUS,
|
|
RECEPTION_MODE_OTHER
|
|
} reception_mode_t;
|
|
|
|
/*!
|
|
* \brief The type describing the modulation parameters for every packet types
|
|
*/
|
|
typedef struct {
|
|
radio_modems_t modem_type; //!< Packet to which the modulation parameters are referring to.
|
|
struct {
|
|
struct {
|
|
uint32_t bit_rate;
|
|
uint32_t fdev;
|
|
radio_mod_shaping_t modulation_shaping;
|
|
uint8_t bandwidth;
|
|
uint32_t operational_frequency;
|
|
} gfsk;
|
|
|
|
struct {
|
|
lora_spread_factors_t spreading_factor; //!< Spreading Factor for the LoRa modulation
|
|
lora_bandwidths_t bandwidth; //!< Bandwidth for the LoRa modulation
|
|
lora_coding_states_t coding_rate; //!< Coding rate for the LoRa modulation
|
|
uint8_t low_datarate_optimization; //!< Indicates if the modem uses the low datarate optimization
|
|
uint32_t operational_frequency;
|
|
} lora;
|
|
} params; //!< Holds the modulation parameters structure
|
|
} modulation_params_t;
|
|
|
|
/*!
|
|
* \brief The type describing the packet parameters for every packet types
|
|
*/
|
|
typedef struct packet_params {
|
|
radio_modems_t modem_type; //!< Packet to which the packet parameters are referring to.
|
|
struct {
|
|
/*!
|
|
* \brief Holds the GFSK packet parameters
|
|
*/
|
|
struct {
|
|
uint16_t preamble_length; //!< The preamble Tx length for GFSK packet type in bit
|
|
radio_preamble_detection_t preamble_min_detect; //!< The preamble Rx length minimal for GFSK packet type
|
|
uint8_t syncword_length; //!< The synchronization word length for GFSK packet type
|
|
radio_address_filter_t addr_comp; //!< Activated SyncWord correlators
|
|
radio_pkt_length_t header_type; //!< If the header is explicit, it will be transmitted in the GFSK packet. If the header is implicit, it will not be transmitted
|
|
uint8_t payload_length; //!< Size of the payload in the GFSK packet
|
|
radio_crc_types_t crc_length; //!< Size of the CRC block in the GFSK packet
|
|
radio_whitening_mode_t whitening_mode;
|
|
} gfsk;
|
|
/*!
|
|
* \brief Holds the LoRa packet parameters
|
|
*/
|
|
struct {
|
|
uint16_t preamble_length; //!< The preamble length is the number of LoRa symbols in the preamble
|
|
lora_pkt_length_t header_type; //!< If the header is explicit, it will be transmitted in the LoRa packet. If the header is implicit, it will not be transmitted
|
|
uint8_t payload_length; //!< Size of the payload in the LoRa packet
|
|
lora_crc_mode_t crc_mode; //!< Size of CRC block in LoRa packet
|
|
lora_IQ_mode_t invert_IQ; //!< Allows to swap IQ for LoRa packet
|
|
} lora;
|
|
} params; //!< Holds the packet parameters structure
|
|
} packet_params_t;
|
|
|
|
/*!
|
|
* \brief Represents the packet status for every packet type
|
|
*/
|
|
typedef struct {
|
|
radio_modems_t modem_type; //!< Packet to which the packet status are referring to.
|
|
struct {
|
|
struct {
|
|
uint8_t rx_status;
|
|
int8_t rssi_avg; //!< The averaged RSSI
|
|
int8_t rssi_sync; //!< The RSSI measured on last packet
|
|
uint32_t freq_error;
|
|
} gfsk;
|
|
struct {
|
|
int8_t rssi_pkt; //!< The RSSI of the last packet
|
|
int8_t snr_pkt; //!< The SNR of the last packet
|
|
int8_t signal_rssi_pkt;
|
|
uint32_t freq_error;
|
|
} lora;
|
|
} params;
|
|
} packet_status_t;
|
|
|
|
/*!
|
|
* \brief Radio driver internal state machine states definition
|
|
*/
|
|
typedef enum {
|
|
RFSWITCH_RX = 0, //!< The radio is in RX
|
|
RFSWITCH_TX = 1 //!< The radio is in TX
|
|
} RFState_t;
|
|
|
|
#endif /* MBED_LORA_RADIO_DRV_STM32WL_RADIO_DRIVER_H_ */
|