mirror of https://github.com/ARMmbed/mbed-os.git
175 lines
9.5 KiB
C
175 lines
9.5 KiB
C
/* mbed Microcontroller Library
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* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __GPIO_INCLUDE_H
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#define __GPIO_INCLUDE_H
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#include <stdint.h>
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#include <stdbool.h>
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#include "TMPM3H6.h"
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#include "objects.h"
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#include "serial_api.h"
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#include "txz_driver_def.h"
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enum BitMode {
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GPIO_PIN_RESET = 0,
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GPIO_PIN_SET,
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};
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enum PortFunction {
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GPIO_Mode_DATA = 0x0, // 0x0: PxDATA
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GPIO_Mode_CR = 0x04, // 0x4: PxCR
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GPIO_Mode_FR1 = 0x08, // 0x8: PxFR1
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GPIO_Mode_FR2 = 0x0C, // 0xC: PxFR2
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GPIO_Mode_FR3 = 0x10, // 0x10: PxFR3
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GPIO_Mode_FR4 = 0x14, // 0x14: PxFR4
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GPIO_Mode_FR5 = 0x18, // 0x18: PxFR5
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GPIO_Mode_FR6 = 0x1C, // 0x1C: PxFR6
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GPIO_Mode_OD = 0x28, // 0x28: PxOD
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GPIO_Mode_PUP = 0x2C, // 0x2C: PxPUP
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GPIO_Mode_PDN = 0x30, // 0x30: PxPDN
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GPIO_Mode_IE = 0x38 // 0x38: PxIE
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};
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// GPIO
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#define PORT_BASE (0x400C0000UL) // Port Register Base Adress
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#define BITBAND_PORT_OFFSET (0x0000100UL) // Port Register Offset Value
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#define BITBAND_PORT_BASE(gr) (PORT_BASE + (uint32_t)((BITBAND_PORT_OFFSET) * (gr)) ) // Operational target Port Adress
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#define BITBAND_PORT_MODE_BASE(base, pinmode) ((uint32_t)(base) + (uint32_t)(pinmode) ) // Operational target Control Register Adress
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#define BITBAND_PORT_SET(base, bitnum) (*((__IO uint32_t *)base) |= (uint32_t)(0x0000001UL<< bitnum)) // Target Pin Bit set
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#define BITBAND_PORT_CLR(base, bitnum) (*((__IO uint32_t *)base) &= ~((uint32_t)(0x0000001UL<< bitnum))) // Target Pin Bit clear
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#define BITBAND_PORT_READ(val, base, bitnum) val = ((*((__IO uint32_t *)base) & (uint32_t)(0x0000001UL<< bitnum)) >> bitnum) // Target Pin Bit read
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#define GPIO_DATA PIN_DATA(0, 2)
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#define CHANNEL_NUM 16
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#define PORT_PIN_NUM 8
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#define PIN_PORT(X) (((uint32_t)(X) >> 3) & 0xF)
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#define PIN_POS(X) ((uint32_t)(X) & 0x7)
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// Pin data, bit 31..16: Pin Function, bit 15..0: Pin Direction
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#define PIN_DATA(FUNC, DIR) (int)(((FUNC) << 16)| ((DIR) << 0))
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#define PIN_FUNC(X) (((X) & 0xFFFF0000) >> 16)
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#define PIN_DIR(X) ((X) & 0xFFFF)
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// SPI
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#define TIMEOUT 1000
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#define INITIAL_SPI_FREQ 1000000
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// I2C
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#define I2CxCR2_I2CM_ENABLE ((uint32_t)0x00000080)
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#define I2CxCR2_SWRES_10 ((uint32_t)0x00000002)
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#define I2CxCR2_SWRES_01 ((uint32_t)0x00000001)
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#define I2CxCR2_START_CONDITION ((uint32_t)0x000000F8)
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#define I2CxCR2_STOP_CONDITION ((uint32_t)0x000000D8)
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#define I2CxCR2_INIT ((uint32_t)0x00000008)
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#define I2CxCR2_PIN_CLEAR ((uint32_t)0x00000010)
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#define I2CxCR2_TRX ((uint32_t)0x00000040)
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#define I2CxST_I2C ((uint32_t)0x00000001)
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#define I2CxST_CLEAR ((uint32_t)0x0000000F)
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#define I2CxCR1_ACK ((uint32_t)0x00000010)
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#define I2CxSR_BB ((uint32_t)0x00000020)
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#define I2CxSR_LRB ((uint32_t)0x00000001)
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#define I2CxOP_RSTA ((uint32_t)0x00000008)
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#define I2CxOP_SREN ((uint32_t)0x00000002)
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#define I2CxOP_MFACK ((uint32_t)0x00000001)
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#define I2CxOP_INIT ((uint32_t)0x00000084)
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#define I2CxIE_CLEAR ((uint32_t)0x00000000)
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#define I2CxPRS_PRCK ((uint32_t)0x0000000F)
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#define I2CxDBR_DB_MASK ((uint32_t)0x000000FF)
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#define I2CxOP_SLAVE_INIT ((uint32_t)0x00000084)
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#define I2CAR_SA_MASK ((uint32_t)0x000000FE)
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#define I2CxSR_TRX ((uint32_t)0x00000040)
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#define I2CxOP_SAST ((uint32_t)0x00000020)
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#define I2CxIE_INTI2C ((uint32_t)0x00000001)
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#define I2C_NO_DATA (0)
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#define I2C_READ_ADDRESSED (1)
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#define I2C_WRITE_ADDRESSED (3)
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#define I2C_ACK (1)
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#define I2C_TIMEOUT (100000)
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// DAC
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#define DAC_START ((uint32_t)0x00000001)
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#define DAC_STOP ((uint32_t)0x00000000)
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// ADC
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#define ADC_12BIT_RANGE 0xFFF
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#define ADC_SCLK_1 ((uint32_t)0x00000000)
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#define ADxMOD0_RCUT_NORMAL ((uint32_t)0x00000000)
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#define ADxMOD0_DACON_ON ((uint32_t)0x00000001)
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#define ADxTSETn_ENINT_DISABLE ((uint32_t)0x00000000)
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#define ADxTSETn_TRGS_SGL ((uint32_t)0x00000040)
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#define ADxCR1_CNTDMEN_DISABLE ((uint32_t)0x00000000)
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#define ADxCR1_SGLDMEN_DISABLE ((uint32_t)0x00000000)
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#define ADxCR1_TRGDMEN_DISABLE ((uint32_t)0x00000000)
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#define ADxCR1_TRGEN_DISABLE ((uint32_t)0x00000000)
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#define ADxCR0_ADEN_DISABLE ((uint32_t)0x00000000)
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#define ADxCR0_ADEN_ENABLE ((uint32_t)0x00000080)
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#define ADxCR0_SGL_ENABLE ((uint32_t)0x00000002)
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#define ADxCR0_CNT_DISABLE ((uint32_t)0x00000000)
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#define ADxST_SNGF_IDLE ((uint32_t)0x00000000)
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#define ADxST_SNGF_RUN ((uint32_t)0x00000004)
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#define ADxREGn_ADRFn_MASK ((uint32_t)0x00000001)
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#define ADxREGn_ADRFn_ON ((uint32_t)0x00000001)
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#define ADxREGn_ADRn_MASK ((uint32_t)0x0000FFF0)
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// Timer & PWM
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#define T32A_INT_MASK ((uint32_t)0x0000000F)
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#define T32A_MODE_32 ((uint32_t)0x00000001)
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#define T32A_PRSCLx_32 ((uint32_t)0x30000000)
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#define T32A_IMUFx_MASK_REQ ((uint32_t)0x00000008)
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#define T32A_IMOFx_MASK_REQ ((uint32_t)0x00000004)
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#define T32A_COUNT_STOP ((uint32_t)0x00000004)
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#define T32A_COUNT_START ((uint32_t)0x00000002)
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#define T32A_RUN_ENABLE ((uint32_t)0x00000001)
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#define T32A_DBG_HALT_STOP ((uint32_t)0x00000002)
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#define T32A_COUNT_DONT_START ((uint32_t)0x00000000)
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#define T32A_RUN_DISABLE ((uint32_t)0x00000000)
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#define T32A_WBF_ENABLE ((uint32_t)0x00100000)
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#define T32A_RELOAD_TREGx ((uint32_t)0x00000700)
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#define T32A_OCRCMPx0_SET ((uint32_t)0x00000001)
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#define T32A_OCRCMPx1_CLR ((uint32_t)0x00000008)
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#define T32A_OCR_DISABLE ((uint32_t)0x00000000)
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#define DEFAULT_PERIOD 0.02f // 20ms
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#define DEFAULT_CLOCK_DIVISION 32
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#define MAX_COUNTER_16B 0xFFFF
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// UART
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#define UART_ENABLE_RX ((uint32_t)0x00000001)
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#define UART_ENABLE_TX ((uint32_t)0x00000002)
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#define UARTxSWRST_SWRSTF_MASK ((uint32_t)0x00000080)
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#define UARTxSWRST_SWRSTF_RUN ((uint32_t)0x00000080)
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#define UARTxSWRST_SWRST_10 ((uint32_t)0x00000002)
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#define UARTxSWRST_SWRST_01 ((uint32_t)0x00000001)
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#define UARTxFIFOCLR_TFCLR_CLEAR ((uint32_t)0x00000002)
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#define UARTxFIFOCLR_RFCLR_CLEAR ((uint32_t)0x00000001)
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#define UART_PLESCALER_1 ((uint32_t)0x00000000)
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#define UART_DIVISION_ENABLE ((uint32_t)0x00800000)
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#define UART_TX_INT_ENABLE ((uint32_t)0x00000040)
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#define UART_RX_INT_ENABLE ((uint32_t)0x00000010)
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#define UART_RX_FIFO_FILL_LEVEL ((uint32_t)0x00000100)
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#define UART_RANGE_K_MIN ((uint32_t)0x00000000)
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#define UART_RANGE_K_MAX ((uint32_t)0x0000003F)
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#define UART_RANGE_N_MIN ((uint32_t)0x00000001)
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#define UART_RANGE_N_MAX ((uint32_t)0x0000FFFF)
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#define UART_NUM 3
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typedef struct {
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uint32_t ken; // Enable/Disable Division Definition
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uint32_t brk; // Division Value K
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uint32_t brn; // Division Value N
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} uart_boudrate_t;
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// Sleep
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#define CG_STBY_MODE_IDLE 0x0
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#define CG_STBY_MODE_STOP1 0x1
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#define EXTERNEL_OSC_MASK 0xFFFFFFF9
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#define IHOSC_CFG_WARM_UP_TIME ((uint64_t)(5000))
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#define IHOSC_CFG_CLOCK ((uint64_t)(10000000))
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#define CGWUPHCR_WUPT_HIGH_MASK ((uint32_t)0xFFF00000)
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#endif // __GPIO_INCLUDE_H
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