mirror of https://github.com/ARMmbed/mbed-os.git
148 lines
4.7 KiB
C++
148 lines
4.7 KiB
C++
/* mbed Microcontroller Library
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* Copyright (c) 2018-2018 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MBED_QSPI_TEST_UTILS_H
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#define MBED_QSPI_TEST_UTILS_H
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#include "flash_configs/flash_configs.h"
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#include "unity/unity.h"
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#define QSPI_NONE (-1)
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enum QspiStatus {
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sOK,
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sError,
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sTimeout,
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sUnknown
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};
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class QspiCommand {
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public:
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void configure(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width,
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qspi_bus_width_t alt_width, qspi_address_size_t addr_size, qspi_alt_size_t alt_size,
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int dummy_cycles = 0);
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void build(int instruction, int address = QSPI_NONE, int alt = QSPI_NONE);
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qspi_command_t *get();
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private:
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qspi_command_t _cmd;
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};
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struct Qspi {
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qspi_t handle;
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QspiCommand cmd;
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};
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// MODE_Command_Address_Data_Alt
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#define MODE_1_1_1 QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE
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#define MODE_1_1_2 QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_DUAL
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#define MODE_1_2_2 QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_DUAL
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#define MODE_1_1_4 QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_QUAD, QSPI_CFG_BUS_SINGLE
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#define MODE_1_4_4 QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_QUAD, QSPI_CFG_BUS_QUAD, QSPI_CFG_BUS_QUAD
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#define WRITE_1_1_1 MODE_1_1_1, QSPI_CMD_WRITE_1IO
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#ifdef QSPI_CMD_WRITE_2IO
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#define WRITE_1_2_2 MODE_1_2_2, QSPI_CMD_WRITE_2IO
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#endif
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#ifdef QSPI_CMD_WRITE_4IO
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#define WRITE_1_4_4 MODE_1_4_4, QSPI_CMD_WRITE_4IO
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#endif
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#define READ_1_1_1 MODE_1_1_1, QSPI_CMD_READ_1IO, QSPI_READ_1IO_DUMMY_CYCLE
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#define READ_1_1_2 MODE_1_1_2, QSPI_CMD_READ_1I2O, QSPI_READ_1I2O_DUMMY_CYCLE
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#define READ_1_2_2 MODE_1_2_2, QSPI_CMD_READ_2IO, QSPI_READ_2IO_DUMMY_CYCLE
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#define READ_1_1_4 MODE_1_1_4, QSPI_CMD_READ_1I4O, QSPI_READ_1I4O_DUMMY_CYCLE
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#define READ_1_4_4 MODE_1_4_4, QSPI_CMD_READ_4IO, QSPI_READ_4IO_DUMMY_CYCLE
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#define ADDR_SIZE_8 QSPI_CFG_ADDR_SIZE_8
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#define ADDR_SIZE_16 QSPI_CFG_ADDR_SIZE_16
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#define ADDR_SIZE_24 QSPI_CFG_ADDR_SIZE_24
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#define ADDR_SIZE_32 QSPI_CFG_ADDR_SIZE_32
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#define ALT_SIZE_8 QSPI_CFG_ALT_SIZE_8
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#define ALT_SIZE_16 QSPI_CFG_ALT_SIZE_16
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#define ALT_SIZE_24 QSPI_CFG_ALT_SIZE_24
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#define ALT_SIZE_32 QSPI_CFG_ALT_SIZE_32
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#define STATUS_REG QSPI_CMD_RDSR
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#define CONFIG_REG0 QSPI_CMD_RDCR0
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#ifdef QSPI_CMD_RDCR1
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#define CONFIG_REG1 QSPI_CMD_RDCR1
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#endif
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#ifdef QSPI_CMD_RDCR2
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#define CONFIG_REG2 QSPI_CMD_RDCR2
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#endif
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#define SECURITY_REG QSPI_CMD_RDSCUR
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#ifndef QSPI_CONFIG_REG_1_SIZE
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#define QSPI_CONFIG_REG_1_SIZE 0
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#endif
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#ifndef QSPI_CONFIG_REG_2_SIZE
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#define QSPI_CONFIG_REG_2_SIZE 0
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#endif
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#define SECTOR_ERASE QSPI_CMD_ERASE_SECTOR
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#define BLOCK_ERASE QSPI_CMD_ERASE_BLOCK_64
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#define SECTOR_ERASE_MAX_TIME QSPI_ERASE_SECTOR_MAX_TIME
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#define BLOCK32_ERASE_MAX_TIME QSPI_ERASE_BLOCK_32_MAX_TIME
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#define BLOCK64_ERASE_MAX_TIME QSPI_ERASE_BLOCK_64_MAX_TIME
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#define PAGE_PROG_MAX_TIME QSPI_PAGE_PROG_MAX_TIME
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#define WRSR_MAX_TIME QSPI_WRSR_MAX_TIME
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#define WAIT_MAX_TIME QSPI_WAIT_MAX_TIME
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qspi_status_t read_register(uint32_t cmd, uint8_t *buf, uint32_t size, Qspi &q);
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qspi_status_t write_register(uint32_t cmd, uint8_t *buf, uint32_t size, Qspi &q);
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QspiStatus flash_wait_for(uint32_t time_us, Qspi &qspi);
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void flash_init(Qspi &qspi);
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qspi_status_t write_enable(Qspi &qspi);
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qspi_status_t write_disable(Qspi &qspi);
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void log_register(uint32_t cmd, uint32_t reg_size, Qspi &qspi, const char *str = NULL);
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qspi_status_t dual_enable(Qspi &qspi);
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qspi_status_t dual_disable(Qspi &qspi);
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qspi_status_t quad_enable(Qspi &qspi);
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qspi_status_t quad_disable(Qspi &qspi);
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qspi_status_t fast_mode_enable(Qspi &qspi);
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qspi_status_t erase(uint32_t erase_cmd, uint32_t flash_addr, Qspi &qspi);
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bool is_dual_cmd(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width);
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bool is_quad_cmd(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width);
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#define WAIT_FOR(timeout, q) TEST_ASSERT_EQUAL_MESSAGE(sOK, flash_wait_for(timeout, q), "flash_wait_for failed!!!")
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#endif // MBED_QSPI_TEST_UTILS_H
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