mirror of https://github.com/ARMmbed/mbed-os.git
210 lines
9.8 KiB
C
210 lines
9.8 KiB
C
/**************************************************************************//**
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* @file pwm.h
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* @version V1.00
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* $Revision: 12 $
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* $Date: 15/06/30 2:52p $
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* @brief NANO100 series PWM driver header file
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*
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* @note
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* Copyright (C) 2013-2014 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#ifndef __PWM_H__
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#define __PWM_H__
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
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@{
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*/
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/** @addtogroup NANO100_PWM_Driver PWM Driver
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@{
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*/
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/** @addtogroup NANO100_PWM_EXPORTED_CONSTANTS PWM Exported Constants
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@{
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*/
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#define PWM_CHANNEL_NUM (4) /*!< PWM channel number \hideinitializer */
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#define PWM_CH0 (0UL) /*!< PWM channel 0 \hideinitializer */
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#define PWM_CH1 (1UL) /*!< PWM channel 1 \hideinitializer */
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#define PWM_CH2 (2UL) /*!< PWM channel 2 \hideinitializer */
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#define PWM_CH3 (3UL) /*!< PWM channel 3 \hideinitializer */
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#define PWM_CH_0_MASK (1UL) /*!< PWM channel 0 mask \hideinitializer */
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#define PWM_CH_1_MASK (2UL) /*!< PWM channel 1 mask \hideinitializer */
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#define PWM_CH_2_MASK (4UL) /*!< PWM channel 2 mask \hideinitializer */
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#define PWM_CH_3_MASK (8UL) /*!< PWM channel 3 mask \hideinitializer */
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#define PWM_CLK_DIV_1 (4UL) /*!< PWM clock divide by 1 \hideinitializer */
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#define PWM_CLK_DIV_2 (0UL) /*!< PWM clock divide by 2 \hideinitializer */
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#define PWM_CLK_DIV_4 (1UL) /*!< PWM clock divide by 4 \hideinitializer */
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#define PWM_CLK_DIV_8 (2UL) /*!< PWM clock divide by 8 \hideinitializer */
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#define PWM_CLK_DIV_16 (3UL) /*!< PWM clock divide by 16 \hideinitializer */
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#define PWM_EDGE_ALIGNED (0UL) /*!< PWM working in edge aligned type \hideinitializer */
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#define PWM_CENTER_ALIGNED (1UL) /*!< PWM working in center aligned type \hideinitializer */
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#define PWM_RISING_LATCH_INT_ENABLE (1UL) /*!< PWM rising latch interrupt enable \hideinitializer */
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#define PWM_FALLING_LATCH_INT_ENABLE (2UL) /*!< PWM falling latch interrupt enable \hideinitializer */
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#define PWM_RISING_FALLING_LATCH_INT_ENABLE (3UL) /*!< PWM rising latch interrupt enable \hideinitializer */
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#define PWM_RISING_LATCH_INT_FLAG (2UL) /*!< PWM rising latch condition happened \hideinitializer */
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#define PWM_FALLING_LATCH_INT_FLAG (4UL) /*!< PWM falling latch condition happened \hideinitializer */
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#define PWM_RISING_FALLING_LATCH_INT_FLAG (6UL) /*!< PWM rising latch condition happened \hideinitializer */
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#define PWM_RISING_LATCH_PDMA_ENABLE (0x10UL) /*!< PWM rising latch PDMA enable \hideinitializer */
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#define PWM_FALLING_LATCH_PDMA_ENABLE (0x20UL) /*!< PWM falling latch PDMA enable \hideinitializer */
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#define PWM_RISING_FALLING_LATCH_PDMA_ENABLE (0x30UL) /*!< PWM rising and falling latch PDMA enable \hideinitializer */
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#define PWM_CAP_PDMA_RFORDER_R (0x1000UL) /*!< PWM captured data transferred by PDMA is rising latch first \hideinitializer */
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#define PWM_CAP_PDMA_RFORDER_F (0UL) /*!< PWM captured data transferred by PDMA is falling latch first \hideinitializer */
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/*@}*/ /* end of group NANO100_PWM_EXPORTED_CONSTANTS */
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/** @addtogroup NANO100_PWM_EXPORTED_FUNCTIONS PWM Exported Functions
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@{
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*/
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/**
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* @brief This macro enable output inverter of specified channel(s)
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
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* Bit 0 represents channel 0, bit 1 represents channel 1...
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* @return None
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* \hideinitializer
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*/
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#define PWM_ENABLE_OUTPUT_INVERTER(pwm, u32ChannelMask)\
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do { \
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uint8_t i; \
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(pwm)->CTL &= ~(PWM_CTL_CH0INV_Msk | PWM_CTL_CH1INV_Msk | PWM_CTL_CH2INV_Msk | PWM_CTL_CH3INV_Msk);\
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for (i = 0; i < PWM_CHANNEL_NUM; i++) { \
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if ( (u32ChannelMask) & (1 << i)) { \
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(pwm)->CTL |= (PWM_CTL_CH0INV_Msk << (i * 8)); \
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} \
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} \
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}while(0)
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/**
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* @brief This macro get captured rising data
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @return None
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* \hideinitializer
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*/
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#define PWM_GET_CAPTURE_RISING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&pwm->CRL0 + 2 * u32ChannelNum))
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/**
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* @brief This macro get captured falling data
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @return None
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* \hideinitializer
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*/
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#define PWM_GET_CAPTURE_FALLING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&pwm->CFL0 + 2 * u32ChannelNum))
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/**
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* @brief This macro set the prescaler of the selected channel
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFF
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* @return None
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* @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed,
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* channel 1 will also be affected.
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* \hideinitializer
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*/
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#define PWM_SET_PRESCALER(pwm, u32ChannelNum, u32Prescaler) \
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(pwm->PRES = (pwm->PRES & ~(PWM_PRES_CP01_Msk << (((u32ChannelNum) >> 1) * 8))) | ((u32Prescaler) << (((u32ChannelNum) >> 1) * 8)))
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/**
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* @brief This macro set the divider of the selected channel
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @param[in] u32Divider Clock divider of specified channel. Valid values are
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* - \ref PWM_CLK_DIV_1
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* - \ref PWM_CLK_DIV_2
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* - \ref PWM_CLK_DIV_4
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* - \ref PWM_CLK_DIV_8
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* - \ref PWM_CLK_DIV_16
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* @return None
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* \hideinitializer
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*/
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#define PWM_SET_DIVIDER(pwm, u32ChannelNum, u32Divider) \
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(pwm->CLKSEL = (pwm->CLKSEL & ~(PWM_CLKSEL_CLKSEL0_Msk << (4 * u32ChannelNum))) | (u32Divider << (4 * u32ChannelNum)))
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/**
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* @brief This macro set the duty of the selected channel
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF
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* @return None
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* @note This new setting will take effect on next PWM period
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* \hideinitializer
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*/
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#define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR) \
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do { \
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*(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CM_Msk; \
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*(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) |= (u32CMR << PWM_DUTY_CM_Pos); \
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}while(0)
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/**
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* @brief This macro set the period of the selected channel
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
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* @return None
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* @note This new setting will take effect on next PWM period
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* @note PWM counter will stop if period length set to 0
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* \hideinitializer
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*/
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#define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR) \
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do { \
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*(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CN_Msk; \
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*(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) |= u32CNR; \
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} while(0)
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uint32_t PWM_ConfigOutputChannel(PWM_T *pwm,
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uint32_t u32ChannelNum,
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uint32_t u32Frequency,
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uint32_t u32DutyCycle);
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uint32_t PWM_ConfigOutputChannel2(PWM_T *pwm,
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uint32_t u32ChannelNum,
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uint32_t u32Frequency,
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uint32_t u32DutyCycle,
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uint32_t u32Frequency2);
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uint32_t PWM_ConfigCaptureChannel (PWM_T *pwm,
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uint32_t u32ChannelNum,
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uint32_t u32UnitTimeNsec,
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uint32_t u32CaptureEdge);
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void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask);
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void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask);
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void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask);
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void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
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void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
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void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
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void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
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void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration);
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void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum);
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void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
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void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
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void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
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uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
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void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType);
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void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum);
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void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
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uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
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void PWM_EnablePDMA(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode);
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void PWM_DisablePDMA(PWM_T *pwm, uint32_t u32ChannelNum);
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/*@}*/ /* end of group NANO100_PWM_EXPORTED_FUNCTIONS */
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/*@}*/ /* end of group NANO100_PWM_Driver */
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/*@}*/ /* end of group NANO100_Device_Driver */
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#ifdef __cplusplus
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}
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#endif
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#endif //__PWM_H__
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/*** (C) COPYRIGHT 2013-2014 Nuvoton Technology Corp. ***/
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