mirror of https://github.com/ARMmbed/mbed-os.git
242 lines
6.9 KiB
C
242 lines
6.9 KiB
C
/**************************************************************************//**
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* @file pdma.c
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* @version V1.00
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* $Revision: 5 $
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* $Date: 14/09/29 3:50p $
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* @brief Nano100 series PDMA driver source file
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*
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* @note
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* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#include "Nano100Series.h"
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/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
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@{
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*/
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/** @addtogroup NANO100_PDMA_Driver PDMA Driver
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@{
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*/
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/** @addtogroup NANO100_PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions
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@{
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*/
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/**
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* @brief PDMA Open
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*
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* @param[in] u32Mask Channel enable bits
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*
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* @return None
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*
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* @details This function enable the PDMA channels.
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*/
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void PDMA_Open(uint32_t u32Mask)
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{
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PDMAGCR->GCRCSR |= (u32Mask << 8);
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}
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/**
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* @brief PDMA Close
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*
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* @param[in] None
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*
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* @return None
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*
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* @details This function disable all PDMA channels.
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*/
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void PDMA_Close(void)
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{
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PDMAGCR->GCRCSR = 0;
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}
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/**
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* @brief Set PDMA Transfer Count
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*
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* @param[in] u32Ch The selected channel
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* @param[in] u32Width Data width. \ref PDMA_WIDTH_8, \ref PDMA_WIDTH_16, or \ref PDMA_WIDTH_32
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* @param[in] u32TransCount Transfer count
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*
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* @return None
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*
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* @details This function set the selected channel data width and transfer count.
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*/
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void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount)
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{
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PDMA_T *pdma;
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pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1)));
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pdma->CSR = (pdma->CSR & ~PDMA_CSR_APB_TWS_Msk) | u32Width;
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switch (u32Width) {
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case PDMA_WIDTH_32:
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pdma->BCR = (u32TransCount << 2);
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break;
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case PDMA_WIDTH_8:
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pdma->BCR = u32TransCount;
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break;
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case PDMA_WIDTH_16:
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pdma->BCR = (u32TransCount << 1);
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break;
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default:
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;
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}
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}
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/**
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* @brief Set PDMA Transfer Address
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*
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* @param[in] u32Ch The selected channel
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* @param[in] u32SrcAddr Source address
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* @param[in] u32SrcCtrl Source control attribute. \ref PDMA_SAR_INC, \ref PDMA_SAR_FIX, or \ref PDMA_SAR_WRA
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* @param[in] u32DstAddr destination address
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* @param[in] u32DstCtrl destination control attribute. \ref PDMA_DAR_INC, \ref PDMA_DAR_FIX, or \ref PDMA_DAR_WRA
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*
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* @return None
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*
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* @details This function set the selected channel source/destination address and attribute.
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*/
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void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)
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{
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PDMA_T *pdma;
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pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1)));
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pdma->SAR = u32SrcAddr;
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pdma->DAR = u32DstAddr;
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pdma->CSR = (pdma->CSR & ~(PDMA_CSR_SAD_SEL_Msk|PDMA_CSR_DAD_SEL_Msk)) | (u32SrcCtrl | u32DstCtrl);
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}
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/**
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* @brief Set PDMA Transfer Mode
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*
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* @param[in] u32Ch The selected channel
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* @param[in] u32Peripheral The selected peripheral.
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* \ref PDMA_SPI0_TX, \ref PDMA_SPI1_TX, \ref PDMA_UART0_TX, \ref PDMA_UART1_TX, \ref PDMA_USB_TX,
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* \ref PDMA_I2S_TX, \ref PDMA_DAC0_TX, \ref PDMA_DAC1_TX, \ref PDMA_SPI2_TX, \ref PDMA_TMR0,
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* \ref PDMA_TMR1, \ref PDMA_TMR2, \ref PDMA_TMR3, \ref PDMA_SPI0_RX, \ref PDMA_SPI1_RX,
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* \ref PDMA_UART0_RX, \ref PDMA_UART1_RX, \ref PDMA_USB_RX, \ref PDMA_I2S_RX, \ref PDMA_ADC,
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* \ref PDMA_SPI2_RX, \ref PDMA_PWM0_CH0, \ref PDMA_PWM0_CH2, \ref PDMA_PWM1_CH0, \ref PDMA_PWM1_CH2,
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* \ref PDMA_MEM
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* @param[in] u32ScatterEn Scatter-gather mode enable
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* @param[in] u32DescAddr Scatter-gather descriptor address
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*
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* @return None
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*
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* @details This function set the selected channel transfer mode. Include peripheral setting.
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*/
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void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr)
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{
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PDMA_T *pdma;
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pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1)));
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switch (u32Ch) {
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case 1:
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PDMAGCR->DSSR0 = (PDMAGCR->DSSR0 & ~DMA_GCR_DSSR0_CH1_SEL_Msk) | (u32Peripheral << DMA_GCR_DSSR0_CH1_SEL_Pos);
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break;
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case 2:
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PDMAGCR->DSSR0 = (PDMAGCR->DSSR0 & ~DMA_GCR_DSSR0_CH2_SEL_Msk) | (u32Peripheral << DMA_GCR_DSSR0_CH2_SEL_Pos);
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break;
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case 3:
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PDMAGCR->DSSR0 = (PDMAGCR->DSSR0 & ~DMA_GCR_DSSR0_CH3_SEL_Msk) | (u32Peripheral << DMA_GCR_DSSR0_CH3_SEL_Pos);
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break;
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case 4:
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PDMAGCR->DSSR1 = (PDMAGCR->DSSR1 & ~DMA_GCR_DSSR1_CH4_SEL_Msk) | u32Peripheral;
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break;
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default:
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;
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}
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if (u32Peripheral == PDMA_MEM)
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pdma->CSR &= ~PDMA_CSR_MODE_SEL_Msk;
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else if (u32Peripheral & 0x10)
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pdma->CSR = (pdma->CSR & ~PDMA_CSR_MODE_SEL_Msk) | 0x4; /* IP to memory */
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else
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pdma->CSR = (pdma->CSR & ~PDMA_CSR_MODE_SEL_Msk) | 0x8; /* memory to IP */
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}
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/**
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* @brief Set PDMA Timeout
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*
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* @param[in] u32Ch The selected channel
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* @param[in] u32OnOff Enable/disable time out function
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* @param[in] u32TimeOutCnt Timeout count
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*
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* @return None
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*
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* @details This function set the timeout count.
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*/
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void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt)
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{
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PDMA_T *pdma;
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pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1)));
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pdma->TCR = (pdma->TCR & ~PDMA_TCR_PDMA_TCR_Msk) | u32TimeOutCnt;
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pdma->CSR = (pdma->CSR & ~PDMA_CSR_TO_EN_Msk) | (u32OnOff << PDMA_CSR_TO_EN_Pos);
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}
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/**
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* @brief Trigger PDMA
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*
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* @param[in] u32Ch The selected channel
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*
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* @return None
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*
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* @details This function trigger the selected channel.
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*/
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void PDMA_Trigger(uint32_t u32Ch)
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{
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PDMA_T *pdma;
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pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1)));
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pdma->CSR |= (PDMA_CSR_TRIG_EN_Msk | PDMA_CSR_PDMACEN_Msk);
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}
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/**
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* @brief Enable Interrupt
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*
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* @param[in] u32Ch The selected channel
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* @param[in] u32Mask The Interrupt Type
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*
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* @return None
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*
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* @details This function enable the selected channel interrupt.
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*/
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void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask)
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{
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PDMA_T *pdma;
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pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1)));
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pdma->IER |= u32Mask;
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}
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/**
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* @brief Disable Interrupt
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*
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* @param[in] u32Ch The selected channel
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* @param[in] u32Mask The Interrupt Type
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*
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* @return None
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*
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* @details This function disable the selected channel interrupt.
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*/
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void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask)
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{
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PDMA_T *pdma;
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pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1)));
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pdma->IER &= ~u32Mask;
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}
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/*@}*/ /* end of group NANO100_PDMA_EXPORTED_FUNCTIONS */
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/*@}*/ /* end of group NANO100_PDMA_Driver */
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/*@}*/ /* end of group NANO100_Device_Driver */
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/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
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