mirror of https://github.com/ARMmbed/mbed-os.git
115 lines
3.6 KiB
C
115 lines
3.6 KiB
C
/**************************************************************************//**
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* @file dac.c
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* @version V1.00
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* $Revision: 4 $
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* $Date: 14/09/08 12:31p $
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* @brief NANO100 series DAC driver source file
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*
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* @note
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* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#include "Nano100Series.h"
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/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
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@{
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*/
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/** @addtogroup NANO100_DAC_Driver DAC Driver
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@{
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*/
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/** @addtogroup NANO100_DAC_EXPORTED_FUNCTIONS DAC Exported Functions
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@{
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*/
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/**
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* @brief This function make a DAC channel ready to convert.
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* @param[in] dac Base address of DAC module.
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* @param[in] u32Ch DAC channel number, could be 0 or 1
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* @param[in] u32TrgSrc Decides the trigger source of specified DAC channel. Valid options are:
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* - \ref DAC_WRITE_DAT_TRIGGER
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* - \ref DAC_PDMA_TRIGGER
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* - \ref DAC_TIMER0_TRIGGER
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* - \ref DAC_TIMER1_TRIGGER
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* - \ref DAC_TIMER2_TRIGGER
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* - \ref DAC_TIMER3_TRIGGER
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* @return None
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* @note This API also set DAC stable time to 2uc according to current PCLK
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*/
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void DAC_Open(DAC_T *dac, uint32_t u32Ch, uint32_t u32TrgSrc)
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{
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uint32_t u32Delay;
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// DAC needs 6 us to stable after power on
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u32Delay = CLK_GetHCLKFreq() * 6 / 1000000;
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if(u32Delay == 0)
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u32Delay++;
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if(u32Ch == 0)
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DAC->CTL0 = (u32Delay << DAC_CTL_DACPWONSTBCNT_Pos) | u32TrgSrc | DAC_CTL_DACEN_Msk;
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else
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DAC->CTL1 = (u32Delay << DAC_CTL_DACPWONSTBCNT_Pos) | u32TrgSrc | DAC_CTL_DACEN_Msk;
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// DAC needs 2 us to stable after convert.
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u32Delay = CLK_GetHCLKFreq() * 2 / 1000000;
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if(u32Delay == 0)
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u32Delay++;
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DAC->COMCTL = (DAC->COMCTL & ~DAC_COMCTL_WAITDACCONV_Msk) | u32Delay;
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}
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/**
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* @brief Disable DAC analog power.
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* @param[in] dac Base address of DAC module.
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* @param[in] u32Ch DAC channel number, could be 0 or 1
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* @return None
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* @details Disable DAC analog power for saving power consumption.
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*/
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void DAC_Close(DAC_T *dac, uint32_t u32Ch)
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{
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if(u32Ch == 0) {
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DAC->CTL0 &= ~DAC_CTL_DACEN_Msk;
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} else {
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DAC->CTL1 &= ~DAC_CTL_DACEN_Msk;
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}
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}
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/**
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* @brief Set delay time for DAC to become stable.
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* @param[in] dac Base address of DAC module.
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* @param[in] u32Delay Decides the DAC conversion settling time, Valid values are between 1~0xFF.
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* @return Success or failed
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* @retval 0 Success
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* @retval -1 Failed, the new setting will cause stable time less than 2us. So new setting is not applied.
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* @details For example, DAC controller clock speed is 12MHz and DAC conversion settling time is 3 us,
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* u32Delay should be given the value 3 * 12 = 36.
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* @note User needs to write appropriate value to meet DAC conversion settling time base on
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* PCLK (APB clock) speed. Minimum delay is 2 us.
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* @note This setting is shared by both DAC channels.
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*/
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int DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay)
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{
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uint32_t u32Dly;
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// DAC needs 2 us to stable after DAC convert, calculate minimal setting
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u32Dly = CLK_GetHCLKFreq() * 2 / 1000000;
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if(u32Dly == 0)
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u32Dly++;
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if(u32Delay < u32Dly) // return error id stable time is shorter than 2us
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return -1;
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DAC->COMCTL = (DAC->COMCTL & ~DAC_COMCTL_WAITDACCONV_Msk) | u32Delay;
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return 0;
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}
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/*@}*/ /* end of group NANO100_DAC_EXPORTED_FUNCTIONS */
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/*@}*/ /* end of group NANO100_DAC_Driver */
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/*@}*/ /* end of group NANO100_Device_Driver */
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/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
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