mirror of https://github.com/ARMmbed/mbed-os.git
203 lines
6.5 KiB
C
203 lines
6.5 KiB
C
/**************************************************************************//**
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* @file adc.c
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* @version V1.00
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* $Revision: 7 $
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* $Date: 14/10/06 6:00p $
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* @brief NANO100 series ADC driver source file
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*
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* @note
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* Copyright (C) 2013-2014 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#include "Nano100Series.h"
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/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
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@{
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*/
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/** @addtogroup NANO100_ADC_Driver ADC Driver
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@{
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*/
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/** @addtogroup NANO100_ADC_EXPORTED_FUNCTIONS ADC Exported Functions
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@{
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*/
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/**
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* @brief This API configures ADC module to be ready for convert the input from selected channel
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* @param[in] adc Base address of ADC module
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* @param[in] u32InputMode Input mode (single-end/differential). Valid values are:
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* - \ref ADC_INPUT_MODE_SINGLE_END
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* - \ref ADC_INPUT_MODE_DIFFERENTIAL
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* @param[in] u32OpMode Operation mode (single/single cycle/continuous). Valid values are:
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* - \ref ADC_OPERATION_MODE_SINGLE
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* - \ref ADC_OPERATION_MODE_SINGLE_CYCLE
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* - \ref ADC_OPERATION_MODE_CONTINUOUS
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* @param[in] u32ChMask Channel enable bit. Each bit corresponds to a input channel. Bit 0 is channel 0, bit 1 is channel 1...
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* @return None
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* @note This API does not turn on ADC power nor does trigger ADC conversion
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*/
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void ADC_Open(ADC_T *adc,
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uint32_t u32InputMode,
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uint32_t u32OpMode,
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uint32_t u32ChMask)
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{
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ADC->CR = (ADC->CR & ~ADC_CR_DIFF_Msk) | u32InputMode;
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ADC->CR = (ADC->CR & ~ADC_CR_ADMD_Msk) | u32OpMode;
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ADC->CR = (ADC->CR & ~ADC_CR_REFSEL_Msk);
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ADC->CHEN = u32ChMask;
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return;
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}
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/**
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* @brief Disable ADC module
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* @param[in] adc Base address of ADC module
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* @return None
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*/
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void ADC_Close(ADC_T *adc)
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{
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SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_ADC_RST_Msk;
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SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_ADC_RST_Msk;
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return;
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}
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/**
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* @brief Configure the hardware trigger condition and enable hardware trigger
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* @param[in] adc Base address of ADC module
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* @param[in] u32Source Decides the hardware trigger source. Valid values are:
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* - \ref ADC_TRIGGER_BY_EXT_PIN
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* @param[in] u32Param While ADC trigger by external pin, this parameter
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* is used to set trigger condition. Valid values are:
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* - \ref ADC_LOW_LEVEL_TRIGGER
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* - \ref ADC_HIGH_LEVEL_TRIGGER
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* - \ref ADC_FALLING_EDGE_TRIGGER
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* - \ref ADC_RISING_EDGE_TRIGGER
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* @return None
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*/
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void ADC_EnableHWTrigger(ADC_T *adc,
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uint32_t u32Source,
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uint32_t u32Param)
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{
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ADC->CR &= ~(ADC_CR_TRGE_Msk | ADC_CR_TRGCOND_Msk | ADC_CR_TRGS_Msk);
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ADC->CR |= u32Source | u32Param | ADC_CR_TRGE_Msk;
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return;
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}
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/**
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* @brief Disable hardware trigger ADC function.
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* @param[in] adc Base address of ADC module
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* @return None
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*/
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void ADC_DisableHWTrigger(ADC_T *adc)
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{
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ADC->CR &= ~(ADC_CR_TRGS_Msk | ADC_CR_TRGCOND_Msk | ADC_CR_TRGE_Msk);
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return;
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}
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/**
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* @brief Config and enable timer trigger
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* @param[in] adc Base address of ADC module
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* @param[in] u32Source Decides which timer trigger ADC. Valid values are: 0 ~ 3
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* @param[in] u32PDMACnt When timer event occurred, PDMA will transfer u32PDMACnt+1 ADC result
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* @return None
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*/
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void ADC_EnableTimerTrigger(ADC_T *adc,
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uint32_t u32Source,
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uint32_t u32PDMACnt)
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{
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ADC->CR &= ~(ADC_CR_TMPDMACNT_Msk | ADC_CR_TMSEL_Msk);
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ADC->CR |= (u32PDMACnt << ADC_CR_TMPDMACNT_Pos) | (u32Source << ADC_CR_TMSEL_Pos) | ADC_CR_TMTRGMOD_Msk;
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return;
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}
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/**
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* @brief Disable timer trigger ADC function.
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* @param[in] adc Base address of ADC module
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* @return None
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*/
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void ADC_DisableTimerTrigger(ADC_T *adc)
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{
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ADC->CR &= ~ADC_CR_TMTRGMOD_Msk;
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return;
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}
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/**
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* @brief Configure the extended sampling time
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* @param[in] adc Base address of ADC module
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* @param[in] u32ChNum The channel number
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* @param[in] u32SampleTime Decides the extend sampling counter. Valid values are 0 ~ 15
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* @return None
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*/
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void ADC_SetExtraSampleTime(ADC_T *adc,
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uint32_t u32ChNum,
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uint32_t u32SampleTime)
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{
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if (u32ChNum < 8)
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ADC->SMPLCNT0 = (ADC->SMPLCNT0 & ~(ADC_SMPLCNT0_CH0SAMPCNT_Msk << (u32ChNum * 4))) | (u32SampleTime << (u32ChNum * 4));
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else if (u32ChNum < 12)
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ADC->SMPLCNT1 = (ADC->SMPLCNT1 & ~(ADC_SMPLCNT1_CH8SAMPCNT_Msk << ((u32ChNum - 8) * 4))) | (u32SampleTime << ((u32ChNum - 8 ) * 4));
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else
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ADC->SMPLCNT1 = (ADC->SMPLCNT1 & ~ADC_SMPLCNT1_INTCHSAMPCNT_Msk) | (u32SampleTime << ADC_SMPLCNT1_INTCHSAMPCNT_Pos);
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}
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/**
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* @brief Enable the interrupt(s) selected by u32Mask parameter.
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* @param[in] adc Base address of ADC module
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* @param[in] u32Mask The combination of interrupt status bits listed below. Each bit
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* corresponds to a interrupt status. This parameter decides which
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* interrupts will be enabled.
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* - \ref ADC_ADF_INT
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* - \ref ADC_CMP0_INT
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* - \ref ADC_CMP1_INT
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* @return None
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*/
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void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask)
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{
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if(u32Mask & ADC_ADF_INT)
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ADC->CR |= ADC_CR_ADIE_Msk;
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if(u32Mask & ADC_CMP0_INT)
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ADC->CMPR0 |= ADC_CMPR_CMPIE_Msk;
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if(u32Mask & ADC_CMP1_INT)
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ADC->CMPR1 |= ADC_CMPR_CMPIE_Msk;
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return;
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}
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/**
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* @brief Disable the interrupt(s) selected by u32Mask parameter.
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* @param[in] adc Base address of ADC module
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* @param[in] u32Mask The combination of interrupt status bits listed below. Each bit
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* corresponds to a interrupt status. This parameter decides which
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* interrupts will be disabled.
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* - \ref ADC_ADF_INT
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* - \ref ADC_CMP0_INT
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* - \ref ADC_CMP1_INT
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* @return None
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*/
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void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask)
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{
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if(u32Mask & ADC_ADF_INT)
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ADC->CR &= ~ADC_CR_ADIE_Msk;
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if(u32Mask & ADC_CMP0_INT)
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ADC->CMPR0 &= ~ADC_CMPR_CMPIE_Msk;
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if(u32Mask & ADC_CMP1_INT)
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ADC->CMPR1 &= ~ADC_CMPR_CMPIE_Msk;
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return;
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}
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/*@}*/ /* end of group NANO100_ADC_EXPORTED_FUNCTIONS */
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/*@}*/ /* end of group NANO100_ADC_Driver */
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/*@}*/ /* end of group NANO100_Device_Driver */
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/*** (C) COPYRIGHT 2013-2014 Nuvoton Technology Corp. ***/
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