mirror of https://github.com/ARMmbed/mbed-os.git
150 lines
4.3 KiB
C
150 lines
4.3 KiB
C
/* mbed Microcontroller Library
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* Copyright (c) 2006-2013 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "spi_api.h"
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#include <math.h>
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#include "cmsis.h"
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#include "pinmap.h"
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#include "clk_freqs.h"
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#include "PeripheralPins.h"
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void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
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// determine the SPI to use
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SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
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SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
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SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
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SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
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SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
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SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
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obj->spi = (SPI_Type*)pinmap_merge(spi_data, spi_cntl);
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MBED_ASSERT((int)obj->spi != NC);
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// enable power and clocking
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switch ((int)obj->spi) {
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case SPI_0: SIM->SCGC5 |= 1 << 11; SIM->SCGC4 |= 1 << 22; break;
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case SPI_1: SIM->SCGC5 |= 1 << 13; SIM->SCGC4 |= 1 << 23; break;
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}
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// enable SPI
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obj->spi->C1 |= SPI_C1_SPE_MASK;
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// pin out the spi pins
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pinmap_pinout(mosi, PinMap_SPI_MOSI);
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pinmap_pinout(miso, PinMap_SPI_MISO);
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pinmap_pinout(sclk, PinMap_SPI_SCLK);
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if (ssel != NC) {
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pinmap_pinout(ssel, PinMap_SPI_SSEL);
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}
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}
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void spi_free(spi_t *obj) {
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// [TODO]
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}
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void spi_format(spi_t *obj, int bits, int mode, int slave) {
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MBED_ASSERT(bits == 8);
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MBED_ASSERT((mode >= 0) && (mode <= 3));
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uint8_t polarity = (mode & 0x2) ? 1 : 0;
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uint8_t phase = (mode & 0x1) ? 1 : 0;
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uint8_t c1_data = ((!slave) << 4) | (polarity << 3) | (phase << 2);
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// clear MSTR, CPOL and CPHA bits
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obj->spi->C1 &= ~(0x7 << 2);
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// write new value
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obj->spi->C1 |= c1_data;
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}
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void spi_frequency(spi_t *obj, int hz) {
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uint32_t error = 0;
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uint32_t p_error = 0xffffffff;
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uint32_t ref = 0;
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uint8_t spr = 0;
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uint8_t ref_spr = 0;
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uint8_t ref_prescaler = 0;
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// bus clk
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uint32_t PCLK = bus_frequency();
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uint8_t prescaler = 1;
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uint8_t divisor = 2;
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for (prescaler = 1; prescaler <= 8; prescaler++) {
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divisor = 2;
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for (spr = 0; spr <= 8; spr++, divisor *= 2) {
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ref = PCLK / (prescaler*divisor);
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if (ref > (uint32_t)hz)
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continue;
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error = hz - ref;
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if (error < p_error) {
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ref_spr = spr;
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ref_prescaler = prescaler - 1;
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p_error = error;
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}
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}
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}
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// set SPPR and SPR
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obj->spi->BR = ((ref_prescaler & 0x7) << 4) | (ref_spr & 0xf);
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}
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static inline int spi_writeable(spi_t * obj) {
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return (obj->spi->S & SPI_S_SPTEF_MASK) ? 1 : 0;
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}
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static inline int spi_readable(spi_t * obj) {
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return (obj->spi->S & SPI_S_SPRF_MASK) ? 1 : 0;
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}
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int spi_master_write(spi_t *obj, int value) {
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// wait tx buffer empty
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while(!spi_writeable(obj));
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obj->spi->D = (value & 0xff);
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// wait rx buffer full
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while (!spi_readable(obj));
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return obj->spi->D & 0xff;
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}
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int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
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char *rx_buffer, int rx_length, char write_fill) {
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int total = (tx_length > rx_length) ? tx_length : rx_length;
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for (int i = 0; i < total; i++) {
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char out = (i < tx_length) ? tx_buffer[i] : write_fill;
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char in = spi_master_write(obj, out);
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if (i < rx_length) {
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rx_buffer[i] = in;
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}
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}
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return total;
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}
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int spi_slave_receive(spi_t *obj) {
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return spi_readable(obj);
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}
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int spi_slave_read(spi_t *obj) {
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return obj->spi->D;
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}
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void spi_slave_write(spi_t *obj, int value) {
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while (!spi_writeable(obj));
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obj->spi->D = value;
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}
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