mirror of https://github.com/ARMmbed/mbed-os.git
198 lines
7.7 KiB
C
198 lines
7.7 KiB
C
/*******************************************************************************
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* Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
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* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Except as contained in this notice, the name of Maxim Integrated
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* Products, Inc. shall not be used except as stated in the Maxim Integrated
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* Products, Inc. Branding Policy.
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*
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* The mere transfer of this software does not imply any licenses
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* of trade secrets, proprietary technology, copyrights, patents,
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* trademarks, maskwork rights, or any other form of intellectual
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* property whatsoever. Maxim Integrated Products, Inc. retains all
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* ownership rights.
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*******************************************************************************
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*/
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#include "max32600.h"
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#include "clkman_regs.h"
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#include "pwrman_regs.h"
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#include "ioman_regs.h"
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#include "trim_regs.h"
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#include "flc_regs.h"
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#include "pwrseq_regs.h"
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#include "dac_regs.h"
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#include "icc_regs.h"
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#include "adc_regs.h"
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/* Application developer should override where necessary with different external HFX source */
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#ifndef __SYSTEM_HFX
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#define __SYSTEM_HFX 8000000
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#endif
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uint32_t SystemCoreClock = 24000000;
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void SystemCoreClockUpdate(void)
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{
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switch ((MXC_CLKMAN->clk_ctrl & MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT) >> MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS) {
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case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO_DIV_8:
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SystemCoreClock = 3000000;
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break;
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case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO:
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case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_PLL_48MHZ_DIV_2:
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SystemCoreClock = 24000000;
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break;
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case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_HFX:
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SystemCoreClock = __SYSTEM_HFX;
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break;
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}
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uint32_t shift = MXC_CLKMAN->clk_ctrl_0_system;
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if (shift) {
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SystemCoreClock = SystemCoreClock >> (shift - 1);
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}
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}
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/* power seq registers */
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static void set_pwr_regs(void)
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{
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uint32_t dac2trim = MXC_DAC2->reg & 0xff00ffff;
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uint32_t dac3trim = MXC_DAC3->reg & 0xff00ffff;
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dac2trim = dac2trim + MXC_TRIM->trim_reg_36;
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dac3trim = dac3trim + MXC_TRIM->trim_reg_37;
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if ((MXC_TRIM->trim_reg_13 != 0) && (MXC_TRIM->trim_reg_13 != 0xFFFFFFFF)) {
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MXC_PWRSEQ->reg5 = MXC_TRIM->trim_reg_13;
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}
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if ((MXC_TRIM->trim_reg_14 != 0) && (MXC_TRIM->trim_reg_14 != 0xFFFFFFFF)) {
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MXC_PWRSEQ->reg6 = MXC_TRIM->trim_reg_14;
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}
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MXC_DAC0->trm = MXC_TRIM->trim_reg_34;
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MXC_DAC1->trm = MXC_TRIM->trim_reg_35;
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MXC_DAC2->reg = dac2trim;
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MXC_DAC3->reg = dac3trim;
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}
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void ICC_Enable(void)
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{
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/* clock gater must be 'on' not 'dynamic' for cache control */
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uint32_t temp = MXC_CLKMAN->clk_gate_ctrl0;
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temp &= ~MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER;
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temp |= (MXC_E_CLKMAN_CLK_GATE_ON << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS);
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MXC_CLKMAN->clk_gate_ctrl0 = temp;
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/* invalidate, wait, enable */
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MXC_ICC->invdt_all = 0xFFFF;
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while(!(MXC_ICC->ctrl_stat & MXC_F_ICC_CTRL_STAT_READY));
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MXC_ICC->ctrl_stat |= MXC_F_ICC_CTRL_STAT_ENABLE;
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/* must invalidate a second time for proper use */
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MXC_ICC->invdt_all = 1;
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/* clock gater 'dynamic' safe again */
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temp = MXC_CLKMAN->clk_gate_ctrl0;
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temp &= ~MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER;
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temp |= (MXC_E_CLKMAN_CLK_GATE_DYNAMIC << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS);
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MXC_CLKMAN->clk_gate_ctrl0 = temp;
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}
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void Trim_RO(void)
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{
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uint32_t reg0;
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uint32_t trim;
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// Save the RTCEN_RUN state and set it
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reg0 = MXC_PWRSEQ->reg0;
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MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
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/* needed if parts are untrimmed */
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if ((MXC_TRIM->trim_reg_13 == 0) || (MXC_TRIM->trim_reg_13 == 0xFFFFFFFF)) {
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MXC_PWRSEQ->reg5 = (MXC_PWRSEQ->reg5 & ~MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF) | (16 << MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS);
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}
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trim = (MXC_PWRSEQ->reg5 & MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF) >> (MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS - 2);
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MXC_ADCCFG->ro_cal1 = (MXC_ADCCFG->ro_cal1 & ~MXC_F_ADC_RO_CAL1_TRM_INIT) |
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((trim << MXC_F_ADC_RO_CAL1_TRM_INIT_POS) & MXC_F_ADC_RO_CAL1_TRM_INIT);
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MXC_ADCCFG->ro_cal0 = (MXC_ADCCFG->ro_cal0 & ~MXC_F_ADC_RO_CAL0_TRM_MU) | (0x04 << MXC_F_ADC_RO_CAL0_TRM_MU_POS);
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MXC_SETBIT(&MXC_ADCCFG->ro_cal0, MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS);
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MXC_SETBIT(&MXC_ADCCFG->ro_cal0, MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS);
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MXC_SETBIT(&MXC_ADCCFG->ro_cal0, MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS);
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SysTick->LOAD = 1635; /* about 50ms, based on a 32KHz systick clock */
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SysTick->VAL = 0;
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SysTick->CTRL = SysTick_CTRL_ENABLE_Msk; /* Enable SysTick Timer */
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while(SysTick->VAL == 0);
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while(!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk));
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SysTick->CTRL = 0;
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trim = (MXC_ADCCFG->ro_cal0 & MXC_F_ADC_RO_CAL0_RO_TRM) >> (MXC_F_ADC_RO_CAL0_RO_TRM_POS + 2);
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MXC_CLRBIT(&MXC_ADCCFG->ro_cal0, MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS);
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MXC_PWRSEQ->reg5 = (MXC_PWRSEQ->reg5 & ~MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF) |
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((trim << MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS) & MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF);
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// Restore the RTCEN_RUN state
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if (!(reg0 & MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN)) {
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MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
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}
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}
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// This function to be implemented by the hal
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extern void low_level_init(void);
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void SystemInit(void)
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{
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set_pwr_regs();
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// Enable instruction cache
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ICC_Enable();
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low_level_init();
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// Clear IO Active
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MXC_PWRMAN->pwr_rst_ctrl = (MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE |
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MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE);
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// Set WUD Clear
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MXC_PWRMAN->pwr_rst_ctrl = (MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE |
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MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE |
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MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR);
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// Set IO Active
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MXC_PWRMAN->pwr_rst_ctrl = (MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE |
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MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE |
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MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE |
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MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED);
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// Clear the first boot flag. Use low_level_init() if special handling is required.
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MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT;
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// Enable the regulator
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MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN;
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// Mask all wakeups
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MXC_PWRSEQ->msk_flags = 0xFFFFFFFF;
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// Set systick to the RTC input 32.768kHz clock, not system clock; this is needed to keep JTAG alive during sleep
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MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE;
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SystemCoreClockUpdate();
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Trim_RO();
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}
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