mirror of https://github.com/ARMmbed/mbed-os.git
225 lines
6.1 KiB
C
225 lines
6.1 KiB
C
/* mbed Microcontroller Library
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* Copyright (c) 2006-2013 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <stddef.h>
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#include "gpio_irq_api.h"
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#include "intc_iodefine.h"
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#include "pinmap.h"
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#include "cmsis.h"
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#include "gpio_addrdefine.h"
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#define CHANNEL_NUM 8
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static void gpio_irq0(void);
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static void gpio_irq1(void);
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static void gpio_irq2(void);
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static void gpio_irq3(void);
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static void gpio_irq4(void);
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static void gpio_irq5(void);
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static void gpio_irq6(void);
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static void gpio_irq7(void);
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static gpio_irq_t *channel_obj[CHANNEL_NUM] = {NULL};
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static gpio_irq_handler irq_handler;
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static const int nIRQn_h = 32;
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extern PinName gpio_multi_guard;
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enum {
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IRQ0,IRQ1,
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IRQ2,IRQ3,
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IRQ4,IRQ5,
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IRQ6,IRQ7,
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} IRQNo;
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static const IRQHandler irq_tbl[CHANNEL_NUM] = {
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&gpio_irq0,
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&gpio_irq1,
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&gpio_irq2,
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&gpio_irq3,
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&gpio_irq4,
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&gpio_irq5,
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&gpio_irq6,
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&gpio_irq7,
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};
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static const PinMap PinMap_IRQ[] = {
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{P1_0, IRQ0, 4}, {P1_1, IRQ1, 4}, {P1_2, IRQ2, 4},
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{P1_3, IRQ3, 4}, {P1_4, IRQ4, 4}, {P1_5, IRQ5, 4},
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{P1_6, IRQ6, 4}, {P1_7, IRQ7, 4}, {P1_8, IRQ2, 3},
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{P1_9, IRQ3, 3}, {P1_10, IRQ4, 3}, {P1_11, IRQ5, 3}, // 11
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{P2_0, IRQ5, 6}, {P2_12, IRQ6, 6}, {P2_13, IRQ7, 8},
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{P2_14, IRQ0, 8}, {P2_15, IRQ1, 8}, // 16
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{P3_0, IRQ2, 3}, {P3_1, IRQ6, 3}, {P3_3, IRQ4, 3},
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{P3_9, IRQ6, 8}, // 20
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{P4_8, IRQ0, 8}, {P4_9, IRQ1, 8}, {P4_10, IRQ2, 8},
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{P4_11, IRQ3, 8}, {P4_12, IRQ4, 8}, {P4_13, IRQ5, 8},
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{P4_14, IRQ6, 8}, {P4_15, IRQ7, 8}, // 28
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{P5_6, IRQ6, 6}, {P5_8, IRQ0, 2}, {P5_9, IRQ2, 4}, // 31
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{P6_0, IRQ5, 6}, {P6_1, IRQ4, 4}, {P6_2, IRQ7, 4},
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{P6_3, IRQ2, 4}, {P6_4, IRQ3, 4}, {P6_8, IRQ0, 8},
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{P6_9, IRQ1, 8}, {P6_10, IRQ2, 8}, {P6_11, IRQ3, 8},
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{P6_12, IRQ4, 8}, {P6_13, IRQ5, 8}, {P6_14, IRQ6, 8},
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{P6_15, IRQ7, 8}, // 44
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{P7_8, IRQ1, 8}, {P7_9, IRQ0, 8}, {P7_10, IRQ2, 8},
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{P7_11, IRQ3, 8}, {P7_12, IRQ4, 8}, {P7_13, IRQ5, 8},
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{P7_14, IRQ6, 8}, // 51
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{P8_2, IRQ0, 5}, {P8_3, IRQ1, 6}, {P8_7, IRQ5, 4},
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{P9_1, IRQ0, 4}, // 55
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{P11_12,IRQ3, 3}, {P11_15,IRQ1, 3}, // 57
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{NC, NC, 0}
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};
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static void handle_interrupt_in(int irq_num) {
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uint16_t irqs;
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uint16_t edge_req;
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gpio_irq_t *obj;
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gpio_irq_event irq_event;
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irqs = INTCIRQRR;
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if (irqs & (1 << irq_num)) {
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obj = channel_obj[irq_num];
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if (obj != NULL) {
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edge_req = ((INTCICR1 >> (obj->ch * 2)) & 3);
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if (edge_req == 1) {
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irq_event = IRQ_FALL;
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} else if (edge_req == 2) {
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irq_event = IRQ_RISE;
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} else {
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uint32_t mask = (1 << (obj->pin & 0x0F));
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__I uint32_t *reg_in = (volatile uint32_t *) PPR((int)PINGROUP(obj->pin));
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if ((*reg_in & mask) == 0) {
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irq_event = IRQ_FALL;
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} else {
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irq_event = IRQ_RISE;
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}
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}
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irq_handler(obj->port, irq_event);
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}
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INTCIRQRR &= ~(1 << irq_num);
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}
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}
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static void gpio_irq0(void) {
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handle_interrupt_in(0);
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}
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static void gpio_irq1(void) {
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handle_interrupt_in(1);
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}
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static void gpio_irq2(void) {
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handle_interrupt_in(2);
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}
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static void gpio_irq3(void) {
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handle_interrupt_in(3);
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}
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static void gpio_irq4(void) {
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handle_interrupt_in(4);
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}
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static void gpio_irq5(void) {
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handle_interrupt_in(5);
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}
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static void gpio_irq6(void) {
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handle_interrupt_in(6);
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}
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static void gpio_irq7(void) {
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handle_interrupt_in(7);
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}
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int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
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int shift;
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if (pin == NC) return -1;
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obj->ch = pinmap_peripheral(pin, PinMap_IRQ);
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obj->pin = (int)pin ;
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obj->port = (int)id ;
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shift = obj->ch*2;
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channel_obj[obj->ch] = obj;
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irq_handler = handler;
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pinmap_pinout(pin, PinMap_IRQ);
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gpio_multi_guard = pin; /* Set multi guard */
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// INTC settings
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InterruptHandlerRegister((IRQn_Type)(nIRQn_h+obj->ch), (void (*)(uint32_t))irq_tbl[obj->ch]);
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INTCICR1 &= ~(0x3 << shift);
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GIC_SetPriority((IRQn_Type)(nIRQn_h+obj->ch), 5);
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obj->int_enable = 1;
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__enable_irq();
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return 0;
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}
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void gpio_irq_free(gpio_irq_t *obj) {
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channel_obj[obj->ch] = NULL;
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}
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void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
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int shift = obj->ch*2;
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uint16_t val = event == IRQ_RISE ? 2 :
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event == IRQ_FALL ? 1 : 0;
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uint16_t work_icr_val;
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/* check edge interrupt setting */
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work_icr_val = INTCICR1;
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if (enable == 1) {
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/* Set interrupt serect */
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work_icr_val |= (val << shift);
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} else {
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/* Clear interrupt serect */
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work_icr_val &= ~(val << shift);
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}
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if ((work_icr_val & (3 << shift)) == 0) {
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/* No edge interrupt setting */
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GIC_DisableIRQ((IRQn_Type)(nIRQn_h+obj->ch));
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/* Clear Interrupt flags */
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INTCIRQRR &= ~(1 << obj->ch);
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INTCICR1 = work_icr_val;
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} else if (obj->int_enable == 1) {
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INTCICR1 = work_icr_val;
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GIC_EnableIRQ((IRQn_Type)(nIRQn_h + obj->ch));
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} else {
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INTCICR1 = work_icr_val;
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}
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}
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void gpio_irq_enable(gpio_irq_t *obj) {
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int shift = obj->ch*2;
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uint16_t work_icr_val = INTCICR1;
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/* check edge interrupt setting */
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if ((work_icr_val & (3 << shift)) != 0) {
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GIC_EnableIRQ((IRQn_Type)(nIRQn_h + obj->ch));
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}
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obj->int_enable = 1;
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}
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void gpio_irq_disable(gpio_irq_t *obj) {
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GIC_DisableIRQ((IRQn_Type)(nIRQn_h + obj->ch));
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obj->int_enable = 0;
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}
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