mirror of https://github.com/ARMmbed/mbed-os.git
86 lines
3.1 KiB
C
86 lines
3.1 KiB
C
/**
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******************************************************************************
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* @file spi.h
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* @brief Inlcude file of a SPI master driver
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* @internal
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* @author ON Semiconductor
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* @version $Rev: $
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* @date $Date: 2016-02-05 $
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******************************************************************************
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* Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
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* All rights reserved. This software and/or documentation is licensed by ON Semiconductor
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* under limited terms and conditions. The terms and conditions pertaining to the software
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* and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
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* (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
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* if applicable the software license agreement. Do not use this software and/or
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* documentation unless you have carefully read and you agree to the limited terms and
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* conditions. By using this software and/or documentation, you agree to the limited
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* terms and conditions.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
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* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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* @endinternal
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*
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* @ingroup spi_h
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*
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* @details
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*
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*/
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#ifndef SPI_H_
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#define SPI_H_
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#include "device.h"
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#include "spi_api.h"
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#if DEVICE_SPI
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Miscellaneous I/O and control operations codes */
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#define SPI_IPC7207_IOCTL_GET_SLAVE_SELECT (0x1) /**< <b>Ioctl request code</b>: Reading slaveSelect register */
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#define SPI_IPC7207_IOCTL_SET_SLAVE_SELECT (0x2) /**< <b>Ioctl request code</b>: Setting slaveSelect register */
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#define SPI_IPC7207_IOCTL_FLUSH (0x3) /**< <b>Ioctl request code</b>: Flushin FIFOs and serial shift registers */
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/* Control register bit positions */
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#define SPI_WORD_WIDTH_BIT_POS 6
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#define SPI_SLAVE_MASTER_BIT_POS 5
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#define SPI_CPOL_BIT_POS 4
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#define SPI_CPHA_BIT_POS 3
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#define SPI_ENDIAN_BIT_POS 2
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#define SPI_SAMPLE_EDGE_BIT_POS 1
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#define SPI_PORT_ENABLE_BIT_POS 0
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/* COntrol register bits */
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#define SPI_ENDIAN_MSB_FIRST 1
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#define SPI_CPOL_IDLE_LOW 0
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#define SPI_CPHA_BEFORE_1ST_EDGE 0
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#define SPI_MASTER_MODE 1
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#define SPI_WORD_WIDTH_8_BITS 0
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#define SPI_SAMPLE_OPP_CLK_EDGE_DATA 0
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#define SPI_SLAVE_SELECT_NORM_BEHAVE 0
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#define SPI_PORT_ENABLE 1
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#define SPI_SLAVE_SELECT_DEFAULT 0x10
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#define SPI_DEFAULT_CONFIG 0x25
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#define SPI_DEFAULT_SPEED 1000000
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#define SPI_BYTE_MASK 0xFF
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extern void fSpiInit(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
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extern void fSpiClose(spi_t *obj);
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extern int fSpiWriteB(spi_t *obj, uint32_t const buf);
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* DEVICE_SPI */
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#endif /* SPI_H_ */
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