mirror of https://github.com/ARMmbed/mbed-os.git
269 lines
7.9 KiB
C
269 lines
7.9 KiB
C
/* mbed Microcontroller Library
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* Copyright (c) 2015-2016 Nuvoton
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "gpio_irq_api.h"
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#if DEVICE_INTERRUPTIN
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#include "gpio_api.h"
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#include "cmsis.h"
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#include "pinmap.h"
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#include "PeripheralPins.h"
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#include "nu_bitutil.h"
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#define NU_MAX_PIN_PER_PORT 16
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struct nu_gpio_irq_var {
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gpio_irq_t * obj_arr[NU_MAX_PIN_PER_PORT];
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IRQn_Type irq_n;
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void (*vec)(void);
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};
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static void gpio_irq_0_vec(void);
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static void gpio_irq_1_vec(void);
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static void gpio_irq_2_vec(void);
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static void gpio_irq_3_vec(void);
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static void gpio_irq_4_vec(void);
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static void gpio_irq_5_vec(void);
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static void gpio_irq_6_vec(void);
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static void gpio_irq_7_vec(void);
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static void gpio_irq_8_vec(void);
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static void gpio_irq(struct nu_gpio_irq_var *var);
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//EINT0_IRQn
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static struct nu_gpio_irq_var gpio_irq_var_arr[] = {
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{{NULL}, GPA_IRQn, gpio_irq_0_vec},
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{{NULL}, GPB_IRQn, gpio_irq_1_vec},
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{{NULL}, GPC_IRQn, gpio_irq_2_vec},
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{{NULL}, GPD_IRQn, gpio_irq_3_vec},
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{{NULL}, GPE_IRQn, gpio_irq_4_vec},
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{{NULL}, GPF_IRQn, gpio_irq_5_vec},
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{{NULL}, GPG_IRQn, gpio_irq_6_vec},
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{{NULL}, GPH_IRQn, gpio_irq_7_vec},
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{{NULL}, GPI_IRQn, gpio_irq_8_vec}
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};
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#define NU_MAX_PORT (sizeof (gpio_irq_var_arr) / sizeof (gpio_irq_var_arr[0]))
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#ifndef MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE
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#define MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE 0
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#endif
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#ifndef MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
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#define MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE_LIST NC
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#endif
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static PinName gpio_irq_debounce_arr[] = {
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MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
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};
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#ifndef MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
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#define MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE GPIO_DBCTL_DBCLKSRC_IRC10K
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#endif
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#ifndef MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
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#define MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16
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#endif
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int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
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{
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if (pin == NC) {
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return -1;
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}
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uint32_t pin_index = NU_PINNAME_TO_PIN(pin);
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uint32_t port_index = NU_PINNAME_TO_PORT(pin);
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if (pin_index >= NU_MAX_PIN_PER_PORT || port_index >= NU_MAX_PORT) {
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return -1;
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}
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obj->pin = pin;
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obj->irq_handler = (uint32_t) handler;
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obj->irq_id = id;
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GPIO_T *gpio_base = NU_PORT_BASE(port_index);
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//gpio_set(pin);
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{
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#if MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE
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// Suppress compiler warning
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(void) gpio_irq_debounce_arr;
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// Configure de-bounce clock source and sampling cycle time
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GPIO_SET_DEBOUNCE_TIME(MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
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GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
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#else
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// Enable de-bounce if the pin is in the de-bounce enable list
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// De-bounce defaults to disabled.
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GPIO_DISABLE_DEBOUNCE(gpio_base, 1 << pin_index);
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PinName *debounce_pos = gpio_irq_debounce_arr;
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PinName *debounce_end = gpio_irq_debounce_arr + sizeof (gpio_irq_debounce_arr) / sizeof (gpio_irq_debounce_arr[0]);
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for (; debounce_pos != debounce_end && *debounce_pos != NC; debounce_pos ++) {
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uint32_t pin_index_debunce = NU_PINNAME_TO_PIN(*debounce_pos);
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uint32_t port_index_debounce = NU_PINNAME_TO_PORT(*debounce_pos);
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if (pin_index == pin_index_debunce &&
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port_index == port_index_debounce) {
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// Configure de-bounce clock source and sampling cycle time
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GPIO_SET_DEBOUNCE_TIME(MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
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GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
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break;
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}
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}
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#endif
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}
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struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
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var->obj_arr[pin_index] = obj;
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// NOTE: InterruptIn requires IRQ enabled by default.
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gpio_irq_enable(obj);
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return 0;
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}
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void gpio_irq_free(gpio_irq_t *obj)
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{
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uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
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uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
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struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
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NVIC_DisableIRQ(var->irq_n);
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NU_PORT_BASE(port_index)->INTEN = 0;
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MBED_ASSERT(pin_index < NU_MAX_PIN_PER_PORT);
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var->obj_arr[pin_index] = NULL;
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}
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void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
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{
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uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
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uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
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GPIO_T *gpio_base = NU_PORT_BASE(port_index);
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switch (event) {
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case IRQ_RISE:
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if (enable) {
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GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_RISING);
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}
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else {
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gpio_base->INTEN &= ~(GPIO_INT_RISING << pin_index);
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}
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break;
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case IRQ_FALL:
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if (enable) {
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GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_FALLING);
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}
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else {
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gpio_base->INTEN &= ~(GPIO_INT_FALLING << pin_index);
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}
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break;
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}
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}
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void gpio_irq_enable(gpio_irq_t *obj)
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{
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//uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
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uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
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struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
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NVIC_SetVector(var->irq_n, (uint32_t) var->vec);
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NVIC_EnableIRQ(var->irq_n);
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}
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void gpio_irq_disable(gpio_irq_t *obj)
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{
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//uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
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uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
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struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
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NVIC_DisableIRQ(var->irq_n);
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}
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static void gpio_irq_0_vec(void)
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{
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gpio_irq(gpio_irq_var_arr + 0);
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}
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static void gpio_irq_1_vec(void)
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{
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gpio_irq(gpio_irq_var_arr + 1);
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}
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static void gpio_irq_2_vec(void)
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{
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gpio_irq(gpio_irq_var_arr + 2);
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}
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static void gpio_irq_3_vec(void)
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{
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gpio_irq(gpio_irq_var_arr + 3);
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}
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static void gpio_irq_4_vec(void)
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{
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gpio_irq(gpio_irq_var_arr + 4);
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}
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static void gpio_irq_5_vec(void)
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{
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gpio_irq(gpio_irq_var_arr + 5);
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}
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static void gpio_irq_6_vec(void)
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{
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gpio_irq(gpio_irq_var_arr + 6);
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}
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static void gpio_irq_7_vec(void)
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{
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gpio_irq(gpio_irq_var_arr + 7);
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}
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static void gpio_irq_8_vec(void)
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{
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gpio_irq(gpio_irq_var_arr + 8);
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}
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static void gpio_irq(struct nu_gpio_irq_var *var)
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{
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uint32_t port_index = var->irq_n - GPA_IRQn;
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GPIO_T *gpio_base = NU_PORT_BASE(port_index);
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uint32_t intsrc = gpio_base->INTSRC;
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uint32_t inten = gpio_base->INTEN;
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while (intsrc) {
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int pin_index = nu_ctz(intsrc);
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gpio_irq_t *obj = var->obj_arr[pin_index];
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if (inten & (GPIO_INT_RISING << pin_index)) {
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if (GPIO_PIN_ADDR(port_index, pin_index)) {
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if (obj->irq_handler) {
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((gpio_irq_handler) obj->irq_handler)(obj->irq_id, IRQ_RISE);
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}
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}
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}
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if (inten & (GPIO_INT_FALLING << pin_index)) {
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if (! GPIO_PIN_ADDR(port_index, pin_index)) {
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if (obj->irq_handler) {
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((gpio_irq_handler) obj->irq_handler)(obj->irq_id, IRQ_FALL);
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}
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}
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}
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intsrc &= ~(1 << pin_index);
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}
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// Clear all interrupt flags
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gpio_base->INTSRC = gpio_base->INTSRC;
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}
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#endif
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