mirror of https://github.com/ARMmbed/mbed-os.git
373 lines
8.8 KiB
C
373 lines
8.8 KiB
C
/* mbed Microcontroller Library
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* Copyright (c) 2006-2015 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "mbed_assert.h"
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#include "i2c_api.h"
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#include "cmsis.h"
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#include "pinmap.h"
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#include "clk_freqs.h"
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#include "PeripheralPins.h"
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static const uint16_t ICR[0x40] = {
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20, 22, 24, 26, 28,
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30, 34, 40, 28, 32,
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36, 40, 44, 48, 56,
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68, 48, 56, 64, 72,
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80, 88, 104, 128, 80,
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96, 112, 128, 144, 160,
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192, 240, 160, 192, 224,
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256, 288, 320, 384, 480,
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320, 384, 448, 512, 576,
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640, 768, 960, 640, 768,
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896, 1024, 1152, 1280, 1536,
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1920, 1280, 1536, 1792, 2048,
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2304, 2560, 3072, 3840
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};
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void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
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// determine the I2C to use
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I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
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I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
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obj->i2c = (I2C_Type*)pinmap_merge(i2c_sda, i2c_scl);
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MBED_ASSERT((int)obj->i2c != NC);
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#if defined(TARGET_K20DX256)
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switch ((int)obj->i2c) {
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case I2C_0: SIM->SCGC4 |= SIM_SCGC4_I2C0_MASK;
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case I2C_1: SIM->SCGC4 |= SIM_SCGC4_I2C1_MASK;
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}
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#else
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SIM->SCGC4 |= SIM_SCGC4_I2C0_MASK;
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#endif
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// set default frequency at 100k
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i2c_frequency(obj, 100000);
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// enable I2C interface
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obj->i2c->C1 |= 0x80;
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pinmap_pinout(sda, PinMap_I2C_SDA);
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pinmap_pinout(scl, PinMap_I2C_SCL);
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/* enable open drain for I2C pins, only port b available */
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uint32_t pin_n = (uint32_t)(sda & 0x7C) >> 2;
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PORTB->PCR[pin_n] |= PORT_PCR_ODE_MASK;
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pin_n = (uint32_t)(scl & 0x7C) >> 2;
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PORTB->PCR[pin_n] |= PORT_PCR_ODE_MASK;
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}
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int i2c_start(i2c_t *obj) {
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// if we are in the middle of a transaction
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// activate the repeat_start flag
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if (obj->i2c->S & I2C_S_BUSY_MASK) {
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obj->i2c->C1 |= 0x04;
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} else {
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obj->i2c->C1 |= I2C_C1_MST_MASK;
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obj->i2c->C1 |= I2C_C1_TX_MASK;
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}
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return 0;
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}
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int i2c_stop(i2c_t *obj) {
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volatile uint32_t n = 0;
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obj->i2c->C1 &= ~I2C_C1_MST_MASK;
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obj->i2c->C1 &= ~I2C_C1_TX_MASK;
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while(obj->i2c->S & I2C_S_BUSY_MASK);
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return 0;
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}
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static int timeout_status_poll(i2c_t *obj, uint32_t mask) {
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uint32_t i, timeout = 100000;
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for (i = 0; i < timeout; i++) {
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if (obj->i2c->S & mask)
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return 0;
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}
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return 1;
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}
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// this function waits the end of a tx transfer and return the status of the transaction:
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// 0: OK ack received
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// 1: OK ack not received
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// 2: failure
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static int i2c_wait_end_tx_transfer(i2c_t *obj) {
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// wait for the interrupt flag
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if (timeout_status_poll(obj, I2C_S_IICIF_MASK)) {
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return 2;
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}
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obj->i2c->S |= I2C_S_IICIF_MASK;
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// wait transfer complete
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if (timeout_status_poll(obj, I2C_S_TCF_MASK)) {
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return 2;
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}
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// check if we received the ACK or not
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return obj->i2c->S & I2C_S_RXAK_MASK ? 1 : 0;
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}
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// this function waits the end of a rx transfer and return the status of the transaction:
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// 0: OK
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// 1: failure
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static int i2c_wait_end_rx_transfer(i2c_t *obj) {
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// wait for the end of the rx transfer
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if (timeout_status_poll(obj, I2C_S_IICIF_MASK)) {
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return 1;
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}
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obj->i2c->S |= I2C_S_IICIF_MASK;
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return 0;
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}
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static void i2c_send_nack(i2c_t *obj) {
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obj->i2c->C1 |= I2C_C1_TXAK_MASK; // NACK
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}
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static void i2c_send_ack(i2c_t *obj) {
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obj->i2c->C1 &= ~I2C_C1_TXAK_MASK; // ACK
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}
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static int i2c_do_write(i2c_t *obj, int value) {
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// write the data
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obj->i2c->D = value;
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// init and wait the end of the transfer
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return i2c_wait_end_tx_transfer(obj);
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}
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static int i2c_do_read(i2c_t *obj, char * data, int last) {
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if (last) {
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i2c_send_nack(obj);
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} else {
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i2c_send_ack(obj);
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}
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*data = (obj->i2c->D & 0xFF);
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// start rx transfer and wait the end of the transfer
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return i2c_wait_end_rx_transfer(obj);
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}
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void i2c_frequency(i2c_t *obj, int hz) {
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uint8_t icr = 0;
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uint8_t mult = 0;
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uint32_t error = 0;
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uint32_t p_error = 0xffffffff;
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uint32_t ref = 0;
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uint8_t i, j;
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// bus clk
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uint32_t PCLK = bus_frequency();
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uint32_t pulse = PCLK / (hz * 2);
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// we look for the values that minimize the error
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// test all the MULT values
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for (i = 1; i < 5; i*=2) {
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for (j = 0; j < 0x40; j++) {
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ref = PCLK / (i*ICR[j]);
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if (ref > (uint32_t)hz)
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continue;
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error = hz - ref;
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if (error < p_error) {
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icr = j;
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mult = i/2;
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p_error = error;
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}
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}
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}
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pulse = icr | (mult << 6);
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// I2C Rate
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obj->i2c->F = pulse;
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}
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int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
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int count;
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char dummy_read, *ptr;
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if (i2c_start(obj)) {
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i2c_stop(obj);
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return I2C_ERROR_BUS_BUSY;
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}
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if (i2c_do_write(obj, (address | 0x01))) {
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i2c_stop(obj);
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return I2C_ERROR_NO_SLAVE;
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}
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// set rx mode
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obj->i2c->C1 &= ~I2C_C1_TX_MASK;
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// Read in bytes
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for (count = 0; count < (length); count++) {
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ptr = (count == 0) ? &dummy_read : &data[count - 1];
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uint8_t stop_ = (count == (length - 1)) ? 1 : 0;
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if (i2c_do_read(obj, ptr, stop_)) {
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i2c_stop(obj);
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return count;
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}
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}
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// If not repeated start, send stop.
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if (stop)
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i2c_stop(obj);
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// last read
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data[count-1] = obj->i2c->D;
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return length;
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}
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int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
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int i;
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if (i2c_start(obj)) {
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i2c_stop(obj);
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return I2C_ERROR_BUS_BUSY;
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}
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if (i2c_do_write(obj, (address & 0xFE))) {
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i2c_stop(obj);
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return I2C_ERROR_NO_SLAVE;
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}
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for (i = 0; i < length; i++) {
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if(i2c_do_write(obj, data[i])) {
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i2c_stop(obj);
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return i;
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}
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}
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if (stop)
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i2c_stop(obj);
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return length;
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}
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void i2c_reset(i2c_t *obj) {
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i2c_stop(obj);
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}
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int i2c_byte_read(i2c_t *obj, int last) {
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char data;
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// set rx mode
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obj->i2c->C1 &= ~I2C_C1_TX_MASK;
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// Setup read
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i2c_do_read(obj, &data, last);
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// set tx mode
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obj->i2c->C1 |= I2C_C1_TX_MASK;
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return obj->i2c->D;
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}
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int i2c_byte_write(i2c_t *obj, int data) {
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// set tx mode
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obj->i2c->C1 |= I2C_C1_TX_MASK;
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return !i2c_do_write(obj, (data & 0xFF));
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}
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#if DEVICE_I2CSLAVE
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void i2c_slave_mode(i2c_t *obj, int enable_slave) {
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if (enable_slave) {
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// set slave mode
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obj->i2c->C1 &= ~I2C_C1_MST_MASK;
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obj->i2c->C1 |= I2C_C1_IICIE_MASK;
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} else {
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// set master mode
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obj->i2c->C1 |= I2C_C1_MST_MASK;
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}
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}
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int i2c_slave_receive(i2c_t *obj) {
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switch(obj->i2c->S) {
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// read addressed
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case 0xE6:
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return 1;
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// write addressed
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case 0xE2:
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return 3;
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default:
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return 0;
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}
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}
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int i2c_slave_read(i2c_t *obj, char *data, int length) {
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uint8_t dummy_read;
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uint8_t * ptr;
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int count;
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// set rx mode
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obj->i2c->C1 &= ~I2C_C1_TX_MASK;
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// first dummy read
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dummy_read = obj->i2c->D;
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if (i2c_wait_end_rx_transfer(obj))
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return 0;
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// read address
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dummy_read = obj->i2c->D;
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if (i2c_wait_end_rx_transfer(obj))
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return 0;
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// read (length - 1) bytes
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for (count = 0; count < (length - 1); count++) {
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data[count] = obj->i2c->D;
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if (i2c_wait_end_rx_transfer(obj))
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return count;
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}
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// read last byte
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ptr = (length == 0) ? &dummy_read : (uint8_t *)&data[count];
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*ptr = obj->i2c->D;
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return (length) ? (count + 1) : 0;
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}
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int i2c_slave_write(i2c_t *obj, const char *data, int length) {
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int i, count = 0;
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// set tx mode
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obj->i2c->C1 |= I2C_C1_TX_MASK;
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for (i = 0; i < length; i++) {
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if (i2c_do_write(obj, data[count++]) == 2)
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return i;
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}
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// set rx mode
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obj->i2c->C1 &= ~I2C_C1_TX_MASK;
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// dummy rx transfer needed
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// otherwise the master cannot generate a stop bit
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obj->i2c->D;
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if (i2c_wait_end_rx_transfer(obj) == 2)
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return count;
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return count;
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}
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void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
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obj->i2c->A1 = address & 0xfe;
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}
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#endif
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