mirror of https://github.com/ARMmbed/mbed-os.git
				
				
				
			
		
			
				
	
	
		
			95 lines
		
	
	
		
			4.6 KiB
		
	
	
	
		
			ArmAsm
		
	
	
			
		
		
	
	
			95 lines
		
	
	
		
			4.6 KiB
		
	
	
	
		
			ArmAsm
		
	
	
/* Copyright (c) 2009 - 2012 ARM LIMITED
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   All rights reserved.
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   Redistribution and use in source and binary forms, with or without
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   modification, are permitted provided that the following conditions are met:
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   - Redistributions of source code must retain the above copyright
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     notice, this list of conditions and the following disclaimer.
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   - Redistributions in binary form must reproduce the above copyright
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     notice, this list of conditions and the following disclaimer in the
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     documentation and/or other materials provided with the distribution.
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   - Neither the name of ARM nor the names of its contributors may be used
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     to endorse or promote products derived from this software without
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     specific prior written permission.
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   *
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   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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   POSSIBILITY OF SUCH DAMAGE.
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   ---------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------
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 *      Functions
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 *---------------------------------------------------------------------------*/
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    .text
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    .global __v7_all_cache
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/*
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 * __STATIC_ASM void __v7_all_cache(uint32_t op) {
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 */
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__v7_all_cache:
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        .arm
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        PUSH    {R4-R11}
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        MRC     p15, 1, R6, c0, c0, 1      /* Read CLIDR */
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        ANDS    R3, R6, #0x07000000        /* Extract coherency level */
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        MOV     R3, R3, LSR #23            /* Total cache levels << 1 */
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        BEQ     Finished                   /* If 0, no need to clean */
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        MOV     R10, #0                    /* R10 holds current cache level << 1 */
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Loop1:  ADD     R2, R10, R10, LSR #1       /* R2 holds cache "Set" position */
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        MOV     R1, R6, LSR R2             /* Bottom 3 bits are the Cache-type for this level */
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        AND     R1, R1, #7                 /* Isolate those lower 3 bits */
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        CMP     R1, #2
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        BLT     Skip                       /* No cache or only instruction cache at this level */
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        MCR     p15, 2, R10, c0, c0, 0     /* Write the Cache Size selection register */
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        ISB                                /* ISB to sync the change to the CacheSizeID reg */
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        MRC     p15, 1, R1, c0, c0, 0      /* Reads current Cache Size ID register */
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        AND     R2, R1, #7                 /* Extract the line length field */
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        ADD     R2, R2, #4                 /* Add 4 for the line length offset (log2 16 bytes) */
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        LDR     R4, =0x3FF
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        ANDS    R4, R4, R1, LSR #3         /* R4 is the max number on the way size (right aligned) */
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        CLZ     R5, R4                     /* R5 is the bit position of the way size increment */
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        LDR     R7, =0x7FFF
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        ANDS    R7, R7, R1, LSR #13        /* R7 is the max number of the index size (right aligned) */
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Loop2:  MOV     R9, R4                     /* R9 working copy of the max way size (right aligned) */
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Loop3:  ORR     R11, R10, R9, LSL R5       /* Factor in the Way number and cache number into R11 */
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        ORR     R11, R11, R7, LSL R2       /* Factor in the Set number */
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        CMP     R0, #0
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        BNE     Dccsw
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        MCR     p15, 0, R11, c7, c6, 2     /* DCISW. Invalidate by Set/Way */
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        B       cont
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Dccsw:  CMP     R0, #1
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        BNE     Dccisw
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        MCR     p15, 0, R11, c7, c10, 2    /* DCCSW. Clean by Set/Way */
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        B       cont
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Dccisw: MCR     p15, 0, R11, c7, c14, 2    /* DCCISW, Clean and Invalidate by Set/Way */
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cont:   SUBS    R9, R9, #1                 /* Decrement the Way number */
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        BGE     Loop3
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        SUBS    R7, R7, #1                 /* Decrement the Set number */
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        BGE     Loop2
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Skip:   ADD     R10, R10, #2               /* increment the cache number */
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        CMP     R3, R10
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        BGT     Loop1
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Finished:
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        DSB
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        POP    {R4-R11}
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        BX     lr
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    .END
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/*----------------------------------------------------------------------------
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 * end of file
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 *---------------------------------------------------------------------------*/
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