mirror of https://github.com/ARMmbed/mbed-os.git
654 lines
18 KiB
C
654 lines
18 KiB
C
/*******************************************************************************
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* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
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* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Except as contained in this notice, the name of Maxim Integrated
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* Products, Inc. shall not be used except as stated in the Maxim Integrated
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* Products, Inc. Branding Policy.
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*
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* The mere transfer of this software does not imply any licenses
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* of trade secrets, proprietary technology, copyrights, patents,
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* trademarks, maskwork rights, or any other form of intellectual
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* property whatsoever. Maxim Integrated Products, Inc. retains all
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* ownership rights.
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*
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* $Date: 2016-07-28 15:01:10 -0500 (Thu, 28 Jul 2016) $
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* $Revision: 23823 $
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*
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******************************************************************************/
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/**
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* @file uart.c
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* @brief UART diver source.
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*/
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/***** Includes *****/
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#include <string.h>
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#include "mxc_assert.h"
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#include "mxc_lock.h"
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#include "mxc_sys.h"
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#include "uart.h"
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/***** Definitions *****/
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#define UART_ERRORS (MXC_F_UART_INTEN_RX_FIFO_OVERFLOW | \
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MXC_F_UART_INTEN_RX_FRAMING_ERR | \
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MXC_F_UART_INTEN_RX_PARITY_ERR)
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#define UART_READ_INTS (MXC_F_UART_INTEN_RX_FIFO_AF | \
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MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY | \
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MXC_F_UART_INTEN_RX_STALLED | \
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UART_ERRORS)
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#define UART_WRITE_INTS (MXC_F_UART_INTEN_TX_UNSTALLED | \
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MXC_F_UART_INTEN_TX_FIFO_AE)
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#define UART_RXFIFO_USABLE (MXC_UART_FIFO_DEPTH-3)
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/***** Globals *****/
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// Saves the state of the non-blocking read requests
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static uart_req_t *rx_states[MXC_CFG_UART_INSTANCES];
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// Saves the state of the non-blocking write requests
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static uart_req_t *tx_states[MXC_CFG_UART_INSTANCES];
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/***** Functions *****/
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static void UART_WriteHandler(mxc_uart_regs_t *uart, uart_req_t *req, int uart_num);
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static void UART_ReadHandler(mxc_uart_regs_t *uart, uart_req_t *req, int uart_num,
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uint32_t flags);
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/******************************************************************************/
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int UART_Init(mxc_uart_regs_t *uart, const uart_cfg_t *cfg, const sys_cfg_uart_t *sys_cfg)
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{
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int err;
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int uart_num;
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uint32_t uart_clk;
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uint8_t baud_shift;
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uint16_t baud_div;
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uint32_t baud, diff_baud;
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uint32_t baud_1, diff_baud_1;
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// Check the input parameters
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uart_num = MXC_UART_GET_IDX(uart);
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MXC_ASSERT(uart_num >= 0);
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// Set system level configurations
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if(sys_cfg != NULL) {
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if ((err = SYS_UART_Init(uart, cfg, sys_cfg)) != E_NO_ERROR) {
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return err;
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}
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}
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// Initialize state pointers
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rx_states[uart_num] = NULL;
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tx_states[uart_num] = NULL;
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// Drain FIFOs and enable UART
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uart->ctrl = 0;
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uart->ctrl = (MXC_F_UART_CTRL_UART_EN | MXC_F_UART_CTRL_TX_FIFO_EN |
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MXC_F_UART_CTRL_RX_FIFO_EN |
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(UART_RXFIFO_USABLE << MXC_F_UART_CTRL_RTS_LEVEL_POS));
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// Configure data size, stop bit, parity, cts, and rts
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uart->ctrl |= ((cfg->size << MXC_F_UART_CTRL_DATA_SIZE_POS) |
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(cfg->extra_stop << MXC_F_UART_CTRL_EXTRA_STOP_POS) |
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(cfg->parity << MXC_F_UART_CTRL_PARITY_POS) |
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(cfg->cts << MXC_F_UART_CTRL_CTS_EN_POS) |
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(cfg->rts << MXC_F_UART_CTRL_RTS_EN_POS));
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// Configure the baud rate and divisor
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uart_clk = SYS_UART_GetFreq(uart);
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MXC_ASSERT(uart_clk > 0);
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baud_shift = 2;
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baud_div = (uart_clk / (cfg->baud * 4));
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// Can not support higher frequencies
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if(!baud_div) {
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return E_NOT_SUPPORTED;
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}
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// Decrease the divisor if baud_div is overflowing
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while(baud_div > 0xFF) {
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if(baud_shift == 0) {
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return E_NOT_SUPPORTED;
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}
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baud_shift--;
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baud_div = (uart_clk / (cfg->baud * (16 >> baud_shift)));
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}
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// Adjust baud_div so we don't overflow with the calculations below
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if(baud_div == 0xFF) {
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baud_div = 0xFE;
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}
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if(baud_div == 0) {
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baud_div = 1;
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}
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// Figure out if the truncation increased the error
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baud = (uart_clk / (baud_div * (16 >> baud_shift)));
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baud_1 = (uart_clk / ((baud_div+1) * (16 >> baud_shift)));
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if(cfg->baud > baud) {
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diff_baud = cfg->baud - baud;
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} else {
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diff_baud = baud - cfg->baud;
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}
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if(cfg->baud > baud_1) {
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diff_baud_1 = cfg->baud - baud_1;
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} else {
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diff_baud_1 = baud_1 - cfg->baud;
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}
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if(diff_baud < diff_baud_1) {
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uart->baud = ((baud_div & MXC_F_UART_BAUD_BAUD_DIVISOR) |
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(baud_shift << MXC_F_UART_BAUD_BAUD_MODE_POS));
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} else {
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uart->baud = (((baud_div+1) & MXC_F_UART_BAUD_BAUD_DIVISOR) |
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(baud_shift << MXC_F_UART_BAUD_BAUD_MODE_POS));
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}
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return E_NO_ERROR;
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}
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/******************************************************************************/
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int UART_Shutdown(mxc_uart_regs_t *uart)
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{
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int uart_num, err;
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uart_req_t *temp_req;
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uart_num = MXC_UART_GET_IDX(uart);
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MXC_ASSERT(uart_num >= 0);
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// Disable and clear interrupts
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uart->inten = 0;
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uart->intfl = uart->intfl;
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// Disable UART and FIFOS
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uart->ctrl &= ~(MXC_F_UART_CTRL_UART_EN | MXC_F_UART_CTRL_TX_FIFO_EN |
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MXC_F_UART_CTRL_RX_FIFO_EN);
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// Call all of the pending callbacks for this UART
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if(rx_states[uart_num] != NULL) {
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// Save the request
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temp_req = rx_states[uart_num];
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// Unlock this UART to read
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mxc_free_lock((uint32_t*)&rx_states[uart_num]);
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// Callback if not NULL
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if(temp_req->callback != NULL) {
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temp_req->callback(temp_req, E_SHUTDOWN);
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}
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}
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if(tx_states[uart_num] != NULL) {
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// Save the request
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temp_req = tx_states[uart_num];
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// Unlock this UART to write
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mxc_free_lock((uint32_t*)&tx_states[uart_num]);
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// Callback if not NULL
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if(temp_req->callback != NULL) {
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temp_req->callback(temp_req, E_SHUTDOWN);
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}
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}
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// Clears system level configurations
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if ((err = SYS_UART_Shutdown(uart)) != E_NO_ERROR) {
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return err;
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}
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return E_NO_ERROR;
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}
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/******************************************************************************/
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int UART_Write(mxc_uart_regs_t *uart, uint8_t* data, int len)
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{
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int num, uart_num;
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mxc_uart_fifo_regs_t *fifo;
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uart_num = MXC_UART_GET_IDX(uart);
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MXC_ASSERT(uart_num >= 0);
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if(data == NULL) {
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return E_NULL_PTR;
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}
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// Make sure the UART has been initialized
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if(!(uart->ctrl & MXC_F_UART_CTRL_UART_EN)) {
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return E_UNINITIALIZED;
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}
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if(!(len > 0)) {
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return E_NO_ERROR;
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}
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// Lock this UART from writing
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while(mxc_get_lock((uint32_t*)&tx_states[uart_num], 1) != E_NO_ERROR) {}
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// Get the FIFO for this UART
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fifo = MXC_UART_GET_FIFO(uart_num);
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num = 0;
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while(num < len) {
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// Wait for TXFIFO to not be full
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while((uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) ==
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MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) {}
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// Write the data to the FIFO
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#if(MXC_UART_REV == 0)
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uart->intfl = MXC_F_UART_INTFL_TX_DONE;
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#endif
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fifo->tx = data[num++];
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}
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// Unlock this UART to write
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mxc_free_lock((uint32_t*)&tx_states[uart_num]);
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return num;
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}
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/******************************************************************************/
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int UART_Read(mxc_uart_regs_t *uart, uint8_t* data, int len, int *num)
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{
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int num_local, remain, uart_num;
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mxc_uart_fifo_regs_t *fifo;
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uart_num = MXC_UART_GET_IDX(uart);
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MXC_ASSERT(uart_num >= 0);
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if(data == NULL) {
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return E_NULL_PTR;
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}
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// Make sure the UART has been initialized
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if(!(uart->ctrl & MXC_F_UART_CTRL_UART_EN)) {
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return E_UNINITIALIZED;
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}
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if(!(len > 0)) {
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return E_NO_ERROR;
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}
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// Lock this UART from reading
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while(mxc_get_lock((uint32_t*)&rx_states[uart_num], 1) != E_NO_ERROR) {}
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// Get the FIFO for this UART
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fifo = MXC_UART_GET_FIFO(uart_num);
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num_local = 0;
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remain = len;
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while(remain) {
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// Save the data in the FIFO
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while((uart->rx_fifo_ctrl & MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY) && remain) {
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data[num_local] = fifo->rx;
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num_local++;
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remain--;
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}
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// Break if there is an error
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if(uart->intfl & UART_ERRORS) {
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break;
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}
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}
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// Save the number of bytes read if pointer is valid
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if(num != NULL) {
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*num = num_local;
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}
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// Check for errors
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if(uart->intfl & MXC_F_UART_INTFL_RX_FIFO_OVERFLOW) {
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// Clear errors and return error code
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uart->intfl = UART_ERRORS;
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// Unlock this UART to read
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mxc_free_lock((uint32_t*)&rx_states[uart_num]);
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return E_OVERFLOW;
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} else if(uart->intfl & (MXC_F_UART_INTFL_RX_FRAMING_ERR |
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MXC_F_UART_INTFL_RX_PARITY_ERR)) {
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// Clear errors and return error code
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uart->intfl = UART_ERRORS;
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// Unlock this UART to read
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mxc_free_lock((uint32_t*)&rx_states[uart_num]);
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return E_COMM_ERR;
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}
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// Unlock this UART to read
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mxc_free_lock((uint32_t*)&rx_states[uart_num]);
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return num_local;
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}
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/******************************************************************************/
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int UART_WriteAsync(mxc_uart_regs_t *uart, uart_req_t *req)
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{
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int uart_num = MXC_UART_GET_IDX(uart);
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MXC_ASSERT(uart_num >= 0);
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// Check the input parameters
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if(req->data == NULL) {
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return E_NULL_PTR;
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}
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// Make sure the UART has been initialized
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if(!(uart->ctrl & MXC_F_UART_CTRL_UART_EN)) {
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return E_UNINITIALIZED;
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}
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if(!(req->len > 0)) {
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return E_NO_ERROR;
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}
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// Attempt to register this write request
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if(mxc_get_lock((uint32_t*)&tx_states[uart_num], (uint32_t)req) != E_NO_ERROR) {
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return E_BUSY;
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}
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// Clear the number of bytes counter
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req->num = 0;
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// Start the write
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UART_WriteHandler(uart, req, uart_num);
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return E_NO_ERROR;
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}
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/******************************************************************************/
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int UART_ReadAsync(mxc_uart_regs_t *uart, uart_req_t *req)
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{
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int uart_num;
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uint32_t flags;
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uart_num = MXC_UART_GET_IDX(uart);
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MXC_ASSERT(uart_num >= 0);
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if(req->data == NULL) {
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return E_NULL_PTR;
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}
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// Make sure the UART has been initialized
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if(!(uart->ctrl & MXC_F_UART_CTRL_UART_EN)) {
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return E_UNINITIALIZED;
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}
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if(!(req->len > 0)) {
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return E_NO_ERROR;
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}
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// Attempt to register this write request
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if(mxc_get_lock((uint32_t*)&rx_states[uart_num], (uint32_t)req) != E_NO_ERROR) {
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return E_BUSY;
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}
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// Clear the number of bytes counter
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req->num = 0;
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// Start the read
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flags = uart->intfl;
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uart->intfl = flags;
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UART_ReadHandler(uart, req, uart_num, flags);
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return E_NO_ERROR;
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}
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/******************************************************************************/
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int UART_AbortAsync(uart_req_t *req)
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{
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int uart_num;
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// Figure out if this was a read or write request, find the request, set to NULL
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for(uart_num = 0; uart_num < MXC_CFG_UART_INSTANCES; uart_num++) {
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if(req == rx_states[uart_num]) {
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// Disable read interrupts, clear flags.
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MXC_UART_GET_UART(uart_num)->inten &= ~UART_READ_INTS;
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MXC_UART_GET_UART(uart_num)->intfl = UART_READ_INTS;
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// Unlock this UART to read
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mxc_free_lock((uint32_t*)&rx_states[uart_num]);
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// Callback if not NULL
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if(req->callback != NULL) {
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req->callback(req, E_ABORT);
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}
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return E_NO_ERROR;
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}
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if(req == tx_states[uart_num]) {
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// Disable write interrupts, clear flags.
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MXC_UART_GET_UART(uart_num)->inten &= ~(UART_WRITE_INTS);
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MXC_UART_GET_UART(uart_num)->intfl = UART_WRITE_INTS;
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// Unlock this UART to write
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mxc_free_lock((uint32_t*)&tx_states[uart_num]);
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// Callback if not NULL
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if(req->callback != NULL) {
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req->callback(req, E_ABORT);
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}
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return E_NO_ERROR;
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}
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}
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return E_BAD_PARAM;
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}
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/******************************************************************************/
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void UART_Handler(mxc_uart_regs_t *uart)
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{
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int uart_num;
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uint32_t flags;
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uart_num = MXC_UART_GET_IDX(uart);
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MXC_ASSERT(uart_num >= 0);
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flags = uart->intfl;
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uart->intfl = flags;
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// Figure out if this UART has an active Read request
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if((rx_states[uart_num] != NULL) && (flags & UART_READ_INTS)) {
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UART_ReadHandler(uart, rx_states[uart_num], uart_num, flags);
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}
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// Figure out if this UART has an active Write request
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if((tx_states[uart_num] != NULL) && (flags & (UART_WRITE_INTS))) {
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UART_WriteHandler(uart, tx_states[uart_num], uart_num);
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}
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}
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/******************************************************************************/
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int UART_Busy(mxc_uart_regs_t *uart)
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{
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int uart_num = MXC_UART_GET_IDX(uart);
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MXC_ASSERT(uart_num >= 0);
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// Check to see if there are any ongoing transactions or if the UART is disabled
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if(((tx_states[uart_num] == NULL) &&
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!(uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) &&
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#if(MXC_UART_REV == 0)
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(uart->intfl & MXC_F_UART_INTFL_TX_DONE)) ||
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#else
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(uart->idle & MXC_F_UART_IDLE_TX_RX_IDLE)) ||
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#endif
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!(uart->ctrl & MXC_F_UART_CTRL_UART_EN)) {
|
|
|
|
return E_NO_ERROR;
|
|
}
|
|
|
|
return E_BUSY;
|
|
}
|
|
|
|
/******************************************************************************/
|
|
int UART_PrepForSleep(mxc_uart_regs_t *uart)
|
|
{
|
|
if(UART_Busy(uart) != E_NO_ERROR) {
|
|
return E_BUSY;
|
|
}
|
|
|
|
// Leave read interrupts enabled, if already enabled
|
|
uart->inten &= UART_READ_INTS;
|
|
|
|
return E_NO_ERROR;
|
|
}
|
|
|
|
/******************************************************************************/
|
|
static void UART_WriteHandler(mxc_uart_regs_t *uart, uart_req_t *req, int uart_num)
|
|
{
|
|
int avail, remain;
|
|
mxc_uart_fifo_regs_t *fifo;
|
|
|
|
// Disable write interrupts
|
|
uart->inten &= ~(UART_WRITE_INTS);
|
|
|
|
// Get the FIFO for this UART
|
|
fifo = MXC_UART_GET_FIFO(uart_num);
|
|
|
|
// Refill the TX FIFO
|
|
avail = UART_NumWriteAvail(uart);
|
|
remain = req->len - req->num;
|
|
|
|
while(avail && remain) {
|
|
|
|
// Write the data to the FIFO
|
|
#if(MXC_UART_REV == 0)
|
|
uart->intfl = MXC_F_UART_INTFL_TX_DONE;
|
|
#endif
|
|
fifo->tx = req->data[req->num++];
|
|
remain--;
|
|
avail--;
|
|
}
|
|
|
|
// All of the bytes have been written to the FIFO
|
|
if(!remain) {
|
|
|
|
// Unlock this UART to write
|
|
mxc_free_lock((uint32_t*)&tx_states[uart_num]);
|
|
|
|
if(req->callback != NULL) {
|
|
req->callback(req, E_NO_ERROR);
|
|
}
|
|
|
|
} else {
|
|
|
|
// Interrupt when there is one byte left in the TXFIFO
|
|
uart->tx_fifo_ctrl = ((MXC_UART_FIFO_DEPTH - 1) << MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS);
|
|
|
|
// Enable almost empty interrupt
|
|
uart->inten |= (MXC_F_UART_INTEN_TX_FIFO_AE);
|
|
}
|
|
}
|
|
|
|
/******************************************************************************/
|
|
static void UART_ReadHandler(mxc_uart_regs_t *uart, uart_req_t *req, int uart_num,
|
|
uint32_t flags)
|
|
{
|
|
int avail, remain;
|
|
mxc_uart_fifo_regs_t *fifo;
|
|
|
|
// Disable interrupts
|
|
uart->inten &= ~UART_READ_INTS;
|
|
|
|
// Get the FIFO for this UART, uart_num
|
|
fifo = MXC_UART_GET_FIFO(uart_num);
|
|
|
|
// Save the data in the FIFO while we still need data
|
|
avail = UART_NumReadAvail(uart);
|
|
remain = req->len - req->num;
|
|
while(avail && remain) {
|
|
req->data[req->num++] = fifo->rx;
|
|
remain--;
|
|
avail--;
|
|
}
|
|
|
|
// Check for errors
|
|
if(flags & MXC_F_UART_INTFL_RX_FIFO_OVERFLOW) {
|
|
|
|
// Unlock this UART to read
|
|
mxc_free_lock((uint32_t*)&rx_states[uart_num]);
|
|
|
|
if(req->callback != NULL) {
|
|
req->callback(req, E_OVERFLOW);
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
if(flags & (MXC_F_UART_INTFL_RX_FRAMING_ERR |
|
|
MXC_F_UART_INTFL_RX_PARITY_ERR)) {
|
|
|
|
// Unlock this UART to read
|
|
mxc_free_lock((uint32_t*)&rx_states[uart_num]);
|
|
|
|
if(req->callback != NULL) {
|
|
req->callback(req, E_COMM_ERR);
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
// Check to see if we're done receiving
|
|
if(remain == 0) {
|
|
|
|
// Unlock this UART to read
|
|
mxc_free_lock((uint32_t*)&rx_states[uart_num]);
|
|
|
|
if(req->callback != NULL) {
|
|
req->callback(req, E_NO_ERROR);
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
if(remain == 1) {
|
|
uart->inten |= (MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY | UART_ERRORS);
|
|
|
|
} else {
|
|
// Set the RX FIFO AF threshold
|
|
if(remain < UART_RXFIFO_USABLE) {
|
|
uart->rx_fifo_ctrl = ((remain - 1) <<
|
|
MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL_POS);
|
|
} else {
|
|
uart->rx_fifo_ctrl = (UART_RXFIFO_USABLE <<
|
|
MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL_POS);
|
|
}
|
|
uart->inten |= (MXC_F_UART_INTEN_RX_FIFO_AF | UART_ERRORS);
|
|
}
|
|
}
|