mirror of https://github.com/ARMmbed/mbed-os.git
733 lines
20 KiB
C
733 lines
20 KiB
C
/* mbed Microcontroller Library
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* Copyright (c) 2006-2015 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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// math.h required for floating point operations for baud rate calculation
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#include "mbed_assert.h"
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#include <math.h>
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#include <string.h>
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#include <stdlib.h>
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#include "serial_api.h"
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#include "cmsis.h"
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#include "pinmap.h"
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#include "gpio_api.h"
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#include "scif_iodefine.h"
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#include "cpg_iodefine.h"
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/******************************************************************************
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* INITIALIZATION
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******************************************************************************/
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#define PCLK (66666666) // Define the peripheral clock P1 frequency.
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#define UART_NUM 8
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#define IRQ_NUM 2
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static void uart0_tx_irq(void);
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static void uart1_tx_irq(void);
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static void uart2_tx_irq(void);
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static void uart3_tx_irq(void);
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static void uart4_tx_irq(void);
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static void uart5_tx_irq(void);
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static void uart6_tx_irq(void);
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static void uart7_tx_irq(void);
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static void uart0_rx_irq(void);
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static void uart1_rx_irq(void);
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static void uart2_rx_irq(void);
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static void uart3_rx_irq(void);
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static void uart4_rx_irq(void);
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static void uart5_rx_irq(void);
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static void uart6_rx_irq(void);
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static void uart7_rx_irq(void);
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#ifdef MAX_PERI
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static const PinMap PinMap_UART_TX[] = {
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{P2_14 , UART0, 6},
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{P4_9 , UART0, 7},
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{P6_9 , UART0, 5},
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{P2_5 , UART1, 6},
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{P4_12 , UART1, 7},
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{P6_12 , UART1, 5},
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{P9_3 , UART1, 4},
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{P3_0 , UART2, 6},
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{P3_1 , UART2, 4},
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{P4_2 , UART2, 5},
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{P4_14 , UART2, 7},
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{P6_3 , UART2, 7},
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{P8_6 , UART2, 7},
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{P3_5 , UART3, 7},
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{P5_3 , UART3, 5},
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{P6_1 , UART3, 7},
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{P8_8 , UART3, 7},
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{P5_0 , UART4, 5},
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{P7_1 , UART4, 4},
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{P8_14 , UART4, 7},
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{P6_6 , UART5, 5},
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{P8_1 , UART5, 4},
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{P8_13 , UART5, 5},
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{P5_6 , UART6, 5},
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{P6_14 , UART6, 4},
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{P7_4 , UART7, 4},
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{NC , NC , 0}
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};
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static const PinMap PinMap_UART_RX[] = {
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{P2_15 , UART0, 6},
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{P4_10 , UART0, 7},
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{P6_10 , UART0, 5},
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{P2_6 , UART1, 6},
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{P4_13 , UART1, 7},
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{P6_13 , UART1, 5},
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{P9_4 , UART1, 4},
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{P3_2 , UART2, 4},
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{P4_3 , UART2, 5},
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{P4_15 , UART2, 7},
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{P6_2 , UART2, 7},
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{P8_4 , UART2, 7},
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{P3_6 , UART3, 7},
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{P5_4 , UART3, 5},
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{P6_0 , UART3, 7},
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{P8_9 , UART3, 7},
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{P5_1 , UART4, 5},
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{P7_2 , UART4, 4},
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{P8_15 , UART4, 7},
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{P6_7 , UART5, 5},
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{P8_2 , UART5, 4},
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{P8_11 , UART5, 5},
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{P5_7 , UART6, 5},
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{P6_15 , UART6, 4},
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{P7_5 , UART7, 4},
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{NC , NC , 0}
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};
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static const PinMap PinMap_UART_CTS[] = {
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{P2_3 , UART1, 6},
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{P9_5 , UART1, 4},
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{P6_3 , UART5, 5},
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{P7_15 , UART5, 4},
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{P7_6 , UART7, 4},
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{NC , NC , 0}
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};
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static const PinMap PinMap_UART_RTS[] = {
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{P2_7 , UART1, 6},
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{P9_6 , UART1, 4},
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{P6_4 , UART5, 5},
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{P8_3 , UART5, 4},
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{P7_7 , UART7, 4},
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{NC , NC , 0}
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};
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#else
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static const PinMap PinMap_UART_TX[] = {
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{P3_0 , UART2, 6},
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{P3_1 , UART2, 4},
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{P4_2 , UART2, 5},
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{P5_3 , UART3, 5},
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{P8_8 , UART3, 7},
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{P5_0 , UART4, 5},
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{P8_14 , UART4, 7},
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{P8_13 , UART5, 5},
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{P5_6 , UART6, 5},
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{NC , NC , 0}
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};
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static const PinMap PinMap_UART_RX[] = {
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{P3_2 , UART2, 4},
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{P4_3 , UART2, 5},
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{P5_4 , UART3, 5},
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{P8_9 , UART3, 7},
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{P5_1 , UART4, 5},
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{P8_15 , UART4, 7},
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{P8_11 , UART5, 5},
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{P5_7 , UART6, 5},
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{NC , NC , 0}
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};
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static const PinMap PinMap_UART_CTS[] = {
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{NC , NC , 0}
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};
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static const PinMap PinMap_UART_RTS[] = {
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{NC , NC , 0}
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};
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#endif
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static const struct st_scif *SCIF[] = SCIF_ADDRESS_LIST;
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static uart_irq_handler irq_handler;
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int stdio_uart_inited = 0;
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serial_t stdio_uart;
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struct serial_global_data_s {
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uint32_t serial_irq_id;
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gpio_t sw_rts, sw_cts;
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uint8_t count, rx_irq_set_flow, rx_irq_set_api;
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};
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static struct serial_global_data_s uart_data[UART_NUM];
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static const IRQn_Type irq_set_tbl[UART_NUM][IRQ_NUM] = {
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{SCIFRXI0_IRQn, SCIFTXI0_IRQn},
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{SCIFRXI1_IRQn, SCIFTXI1_IRQn},
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{SCIFRXI2_IRQn, SCIFTXI2_IRQn},
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{SCIFRXI3_IRQn, SCIFTXI3_IRQn},
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{SCIFRXI4_IRQn, SCIFTXI4_IRQn},
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{SCIFRXI5_IRQn, SCIFTXI5_IRQn},
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{SCIFRXI6_IRQn, SCIFTXI6_IRQn},
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{SCIFRXI7_IRQn, SCIFTXI7_IRQn}
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};
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static const IRQHandler hander_set_tbl[UART_NUM][IRQ_NUM] = {
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{uart0_rx_irq, uart0_tx_irq},
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{uart1_rx_irq, uart1_tx_irq},
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{uart2_rx_irq, uart2_tx_irq},
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{uart3_rx_irq, uart3_tx_irq},
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{uart4_rx_irq, uart4_tx_irq},
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{uart5_rx_irq, uart5_tx_irq},
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{uart6_rx_irq, uart6_tx_irq},
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{uart7_rx_irq, uart7_tx_irq}
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};
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static __IO uint16_t *SCSCR_MATCH[] = {
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&SCSCR_0,
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&SCSCR_1,
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&SCSCR_2,
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&SCSCR_3,
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&SCSCR_4,
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&SCSCR_5,
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&SCSCR_6,
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&SCSCR_7,
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};
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static __IO uint16_t *SCFSR_MATCH[] = {
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&SCFSR_0,
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&SCFSR_1,
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&SCFSR_2,
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&SCFSR_3,
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&SCFSR_4,
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&SCFSR_5,
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&SCFSR_6,
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&SCFSR_7,
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};
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void serial_init(serial_t *obj, PinName tx, PinName rx) {
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volatile uint8_t dummy ;
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int is_stdio_uart = 0;
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// determine the UART to use
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uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
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uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
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uint32_t uart = pinmap_merge(uart_tx, uart_rx);
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MBED_ASSERT((int)uart != NC);
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obj->uart = (struct st_scif *)SCIF[uart];
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// enable power
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switch (uart) {
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case UART0:
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CPG.STBCR4 &= ~(1 << 7);
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break;
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case UART1:
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CPG.STBCR4 &= ~(1 << 6);
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break;
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case UART2:
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CPG.STBCR4 &= ~(1 << 5);
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break;
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case UART3:
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CPG.STBCR4 &= ~(1 << 4);
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break;
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case UART4:
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CPG.STBCR4 &= ~(1 << 3);
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break;
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case UART5:
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CPG.STBCR4 &= ~(1 << 2);
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break;
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case UART6:
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CPG.STBCR4 &= ~(1 << 1);
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break;
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case UART7:
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CPG.STBCR4 &= ~(1 << 0);
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break;
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}
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dummy = CPG.STBCR4;
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/* if this uart has been previously configured to tx, wait tx completion befor loading new configuration */
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if(obj->uart->SCSCR & 0xA0)
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while(!(obj->uart->SCFSR & 0x0040));
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/* ==== SCIF initial setting ==== */
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/* ---- Serial control register (SCSCR) setting ---- */
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/* B'00 : Internal CLK */
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obj->uart->SCSCR = 0x0000u; /* SCIF transmitting and receiving operations stop */
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/* ---- FIFO control register (SCFCR) setting ---- */
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/* Transmit FIFO reset & Receive FIFO data register reset */
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obj->uart->SCFCR = 0x0006;
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/* ---- Serial status register (SCFSR) setting ---- */
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dummy = obj->uart->SCFSR;
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obj->uart->SCFSR = (dummy & 0xFF6Cu); /* ER,BRK,DR bit clear */
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/* ---- Line status register (SCLSR) setting ---- */
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/* ORER bit clear */
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obj->uart->SCLSR = 0;
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/* ---- Serial extension mode register (SCEMR) setting ----
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b7 BGDM - Baud rate generator double-speed mode : Normal mode
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b0 ABCS - Base clock select in asynchronous mode : Base clock is 16 times the bit rate */
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obj->uart->SCEMR = 0x0000u;
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/* ---- Bit rate register (SCBRR) setting ---- */
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serial_baud (obj, 9600);
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serial_format(obj, 8, ParityNone, 1);
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/* ---- FIFO control register (SCFCR) setting ---- */
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obj->uart->SCFCR = 0x0030u;
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/* ---- Serial port register (SCSPTR) setting ----
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b1 SPB2IO - Serial port break output : disabled
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b0 SPB2DT - Serial port break data : High-level */
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obj->uart->SCSPTR = 0x0003u; // SPB2IO = 1, SPB2DT = 1
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/* ---- Line status register (SCLSR) setting ----
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b0 ORER - Overrun error detect : clear */
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if (obj->uart->SCLSR & 0x0001) {
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obj->uart->SCLSR = 0u; // ORER clear
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}
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// pinout the chosen uart
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pinmap_pinout(tx, PinMap_UART_TX);
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pinmap_pinout(rx, PinMap_UART_RX);
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switch (uart) {
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case UART0:
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obj->index = 0;
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break;
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case UART1:
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obj->index = 1;
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break;
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case UART2:
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obj->index = 2;
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break;
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case UART3:
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obj->index = 3;
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break;
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case UART4:
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obj->index = 4;
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break;
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case UART5:
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obj->index = 5;
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break;
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case UART6:
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obj->index = 6;
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break;
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case UART7:
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obj->index = 7;
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break;
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}
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uart_data[obj->index].sw_rts.pin = NC;
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uart_data[obj->index].sw_cts.pin = NC;
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/* ---- Serial control register (SCSCR) setting ---- */
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/* Setting the TE and RE bits enables the TxD and RxD pins to be used. */
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obj->uart->SCSCR = (((uart_tx != (uint32_t)NC)? 0xA0 : 0) | ((uart_rx != (uint32_t)NC)? 0x50 : 0 )); //0x00F0;
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is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
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if (is_stdio_uart) {
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stdio_uart_inited = 1;
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memcpy(&stdio_uart, obj, sizeof(serial_t));
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}
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}
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void serial_free(serial_t *obj) {
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uart_data[obj->index].serial_irq_id = 0;
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}
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// serial_baud
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// set the baud rate, taking in to account the current SystemFrequency
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void serial_baud(serial_t *obj, int baudrate) {
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uint16_t DL;
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obj->uart->SCSMR &= ~0x0003;
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if (baudrate > 32552) {
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obj->uart->SCEMR = 0x0081; // BGDM = 1, ABCS = 1
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DL = PCLK / (8 * baudrate);
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if (DL > 0) {
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DL--;
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}
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obj->uart->SCBRR = (uint8_t)DL;
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} else if (baudrate > 16276) {
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obj->uart->SCEMR = 0x0080; // BGDM = 1
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obj->uart->SCBRR = PCLK / (16 * baudrate) - 1;
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} else if (baudrate > 8138) {
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obj->uart->SCEMR = 0x0000;
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obj->uart->SCBRR = PCLK / (32 * baudrate) - 1;
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} else if (baudrate > 4169) {
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obj->uart->SCSMR |= 0x0001;
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obj->uart->SCEMR = 0x0080; // BGDM = 1
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obj->uart->SCBRR = PCLK / (64 * baudrate) - 1;
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} else if (baudrate > 2034) {
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obj->uart->SCSMR |= 0x0001;
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obj->uart->SCEMR = 0x0000;
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obj->uart->SCBRR = PCLK / (128 * baudrate) - 1;
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} else if (baudrate > 1017) {
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obj->uart->SCSMR |= 0x0002;
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obj->uart->SCEMR = 0x0080; // BGDM = 1
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obj->uart->SCBRR = PCLK / (256 * baudrate) - 1;
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} else if (baudrate > 508) {
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obj->uart->SCSMR |= 0x0002;
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obj->uart->SCEMR = 0x0000;
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obj->uart->SCBRR = PCLK / (512 * baudrate) - 1;
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} else if (baudrate > 254) {
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obj->uart->SCSMR |= 0x0003;
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obj->uart->SCEMR = 0x0080; // BGDM = 1
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obj->uart->SCBRR = PCLK / (1024 * baudrate) - 1;
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} else if (baudrate > 127) {
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obj->uart->SCSMR |= 0x0003;
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obj->uart->SCEMR = 0x0000;
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obj->uart->SCBRR = PCLK / (2048 * baudrate) - 1;
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} else {
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obj->uart->SCSMR |= 0x0003;
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obj->uart->SCEMR = 0x0000;
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obj->uart->SCBRR = 0xFFu;
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}
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}
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void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
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int parity_enable;
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int parity_select;
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MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits
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MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 5: 5 data bits ... 3: 8 data bits
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MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) ||
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(parity == ParityForced1) || (parity == ParityForced0));
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stop_bits = (stop_bits == 1)? 0:
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(stop_bits == 2)? 1:
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0; // must not to be
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data_bits = (data_bits == 8)? 0:
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(data_bits == 7)? 1:
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0; // must not to be
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switch (parity) {
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case ParityNone:
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parity_enable = 0;
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parity_select = 0;
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break;
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case ParityOdd:
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parity_enable = 1;
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parity_select = 1;
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break;
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case ParityEven:
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parity_enable = 1;
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parity_select = 0;
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break;
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case ParityForced1:
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case ParityForced0:
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default:
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parity_enable = 0;
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parity_select = 0;
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break;
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}
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obj->uart->SCSMR = data_bits << 6
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| parity_enable << 5
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| parity_select << 4
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| stop_bits << 3;
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}
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/******************************************************************************
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* INTERRUPTS HANDLING
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******************************************************************************/
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static void uart_tx_irq(IRQn_Type irq_num, uint32_t index) {
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__IO uint16_t *dmy_rd_scscr;
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__IO uint16_t *dmy_rd_scfsr;
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dmy_rd_scscr = SCSCR_MATCH[index];
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*dmy_rd_scscr &= 0x007B; // Clear TIE and Write to bit15~8,2 is always 0
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dmy_rd_scfsr = SCFSR_MATCH[index];
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*dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0020); // Clear TDFE
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irq_handler(uart_data[index].serial_irq_id, TxIrq);
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}
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static void uart_rx_irq(IRQn_Type irq_num, uint32_t index) {
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__IO uint16_t *dmy_rd_scscr;
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__IO uint16_t *dmy_rd_scfsr;
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|
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|
dmy_rd_scscr = SCSCR_MATCH[index];
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*dmy_rd_scscr &= 0x00B3; // Clear RIE,REIE and Write to bit15~8,2 is always 0
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dmy_rd_scfsr = SCFSR_MATCH[index];
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*dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0003); // Clear RDF,DR
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|
|
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irq_handler(uart_data[index].serial_irq_id, RxIrq);
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|
}
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|
|
|
/* TX handler */
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|
static void uart0_tx_irq(void) {
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|
uart_tx_irq(SCIFTXI0_IRQn, 0);
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|
}
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|
static void uart1_tx_irq(void) {
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|
uart_tx_irq(SCIFTXI1_IRQn, 1);
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|
}
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|
static void uart2_tx_irq(void) {
|
|
uart_tx_irq(SCIFTXI2_IRQn, 2);
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|
}
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|
static void uart3_tx_irq(void) {
|
|
uart_tx_irq(SCIFTXI3_IRQn, 3);
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|
}
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|
static void uart4_tx_irq(void) {
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|
uart_tx_irq(SCIFTXI4_IRQn, 4);
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|
}
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|
static void uart5_tx_irq(void) {
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|
uart_tx_irq(SCIFTXI5_IRQn, 5);
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|
}
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|
static void uart6_tx_irq(void) {
|
|
uart_tx_irq(SCIFTXI6_IRQn, 6);
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|
}
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|
static void uart7_tx_irq(void) {
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|
uart_tx_irq(SCIFTXI7_IRQn, 7);
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|
}
|
|
/* RX handler */
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|
static void uart0_rx_irq(void) {
|
|
uart_rx_irq(SCIFRXI0_IRQn, 0);
|
|
}
|
|
static void uart1_rx_irq(void) {
|
|
uart_rx_irq(SCIFRXI1_IRQn, 1);
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|
}
|
|
static void uart2_rx_irq(void) {
|
|
uart_rx_irq(SCIFRXI2_IRQn, 2);
|
|
}
|
|
static void uart3_rx_irq(void) {
|
|
uart_rx_irq(SCIFRXI3_IRQn, 3);
|
|
}
|
|
static void uart4_rx_irq(void) {
|
|
uart_rx_irq(SCIFRXI4_IRQn, 4);
|
|
}
|
|
static void uart5_rx_irq(void) {
|
|
uart_rx_irq(SCIFRXI5_IRQn, 5);
|
|
}
|
|
static void uart6_rx_irq(void) {
|
|
uart_rx_irq(SCIFRXI6_IRQn, 6);
|
|
}
|
|
static void uart7_rx_irq(void) {
|
|
uart_rx_irq(SCIFRXI7_IRQn, 7);
|
|
}
|
|
|
|
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
|
|
irq_handler = handler;
|
|
uart_data[obj->index].serial_irq_id = id;
|
|
}
|
|
|
|
static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) {
|
|
IRQn_Type IRQn;
|
|
IRQHandler handler;
|
|
|
|
IRQn = irq_set_tbl[obj->index][irq];
|
|
handler = hander_set_tbl[obj->index][irq];
|
|
|
|
if ((obj->index >= 0) && (obj->index <= 7)) {
|
|
if (enable) {
|
|
InterruptHandlerRegister(IRQn, (void (*)(uint32_t))handler);
|
|
GIC_SetPriority(IRQn, 5);
|
|
GIC_EnableIRQ(IRQn);
|
|
} else {
|
|
GIC_DisableIRQ(IRQn);
|
|
}
|
|
}
|
|
}
|
|
|
|
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
|
|
if (RxIrq == irq) {
|
|
uart_data[obj->index].rx_irq_set_api = enable;
|
|
}
|
|
serial_irq_set_internal(obj, irq, enable);
|
|
}
|
|
|
|
static void serial_flow_irq_set(serial_t *obj, uint32_t enable) {
|
|
uart_data[obj->index].rx_irq_set_flow = enable;
|
|
serial_irq_set_internal(obj, RxIrq, enable);
|
|
}
|
|
|
|
/******************************************************************************
|
|
* READ/WRITE
|
|
******************************************************************************/
|
|
int serial_getc(serial_t *obj) {
|
|
uint16_t err_read;
|
|
int data;
|
|
int was_masked;
|
|
|
|
#if defined ( __ICCARM__ )
|
|
was_masked = __disable_irq_iar();
|
|
#else
|
|
was_masked = __disable_irq();
|
|
#endif /* __ICCARM__ */
|
|
if (obj->uart->SCFSR & 0x93) {
|
|
err_read = obj->uart->SCFSR;
|
|
obj->uart->SCFSR = (err_read & ~0x93);
|
|
}
|
|
obj->uart->SCSCR |= 0x0040; // Set RIE
|
|
if (!was_masked) {
|
|
__enable_irq();
|
|
}
|
|
|
|
if (obj->uart->SCLSR & 0x0001) {
|
|
obj->uart->SCLSR = 0u; // ORER clear
|
|
}
|
|
|
|
while (!serial_readable(obj));
|
|
data = obj->uart->SCFRDR & 0xff;
|
|
|
|
#if defined ( __ICCARM__ )
|
|
was_masked = __disable_irq_iar();
|
|
#else
|
|
was_masked = __disable_irq();
|
|
#endif /* __ICCARM__ */
|
|
err_read = obj->uart->SCFSR;
|
|
obj->uart->SCFSR = (err_read & 0xfffD); // Clear RDF
|
|
if (!was_masked) {
|
|
__enable_irq();
|
|
}
|
|
|
|
if (err_read & 0x80) {
|
|
data = -1; //err
|
|
}
|
|
return data;
|
|
}
|
|
|
|
void serial_putc(serial_t *obj, int c) {
|
|
uint16_t dummy_read;
|
|
int was_masked;
|
|
|
|
#if defined ( __ICCARM__ )
|
|
was_masked = __disable_irq_iar();
|
|
#else
|
|
was_masked = __disable_irq();
|
|
#endif /* __ICCARM__ */
|
|
obj->uart->SCSCR |= 0x0080; // Set TIE
|
|
if (!was_masked) {
|
|
__enable_irq();
|
|
}
|
|
while (!serial_writable(obj));
|
|
obj->uart->SCFTDR = c;
|
|
#if defined ( __ICCARM__ )
|
|
was_masked = __disable_irq_iar();
|
|
#else
|
|
was_masked = __disable_irq();
|
|
#endif /* __ICCARM__ */
|
|
dummy_read = obj->uart->SCFSR;
|
|
obj->uart->SCFSR = (dummy_read & 0xff9f); // Clear TEND/TDFE
|
|
if (!was_masked) {
|
|
__enable_irq();
|
|
}
|
|
uart_data[obj->index].count++;
|
|
}
|
|
|
|
int serial_readable(serial_t *obj) {
|
|
return ((obj->uart->SCFSR & 0x02) != 0); // RDF
|
|
}
|
|
|
|
int serial_writable(serial_t *obj) {
|
|
return ((obj->uart->SCFSR & 0x20) != 0); // TDFE
|
|
}
|
|
|
|
void serial_clear(serial_t *obj) {
|
|
int was_masked;
|
|
#if defined ( __ICCARM__ )
|
|
was_masked = __disable_irq_iar();
|
|
#else
|
|
was_masked = __disable_irq();
|
|
#endif /* __ICCARM__ */
|
|
|
|
obj->uart->SCFCR |= 0x06; // TFRST = 1, RFRST = 1
|
|
obj->uart->SCFCR &= ~0x06; // TFRST = 0, RFRST = 0
|
|
obj->uart->SCFSR &= ~0x0093u; // ER, BRK, RDF, DR = 0
|
|
|
|
if (!was_masked) {
|
|
__enable_irq();
|
|
}
|
|
}
|
|
|
|
void serial_pinout_tx(PinName tx) {
|
|
pinmap_pinout(tx, PinMap_UART_TX);
|
|
}
|
|
|
|
void serial_break_set(serial_t *obj) {
|
|
int was_masked;
|
|
#if defined ( __ICCARM__ )
|
|
was_masked = __disable_irq_iar();
|
|
#else
|
|
was_masked = __disable_irq();
|
|
#endif /* __ICCARM__ */
|
|
// TxD Output(L)
|
|
obj->uart->SCSPTR &= ~0x0001u; // SPB2DT = 0
|
|
obj->uart->SCSCR &= ~0x0020u; // TE = 0 (Output disable)
|
|
if (!was_masked) {
|
|
__enable_irq();
|
|
}
|
|
}
|
|
|
|
void serial_break_clear(serial_t *obj) {
|
|
int was_masked;
|
|
#if defined ( __ICCARM__ )
|
|
was_masked = __disable_irq_iar();
|
|
#else
|
|
was_masked = __disable_irq();
|
|
#endif /* __ICCARM__ */
|
|
obj->uart->SCSCR |= 0x0020u; // TE = 1 (Output enable)
|
|
obj->uart->SCSPTR |= 0x0001u; // SPB2DT = 1
|
|
if (!was_masked) {
|
|
__enable_irq();
|
|
}
|
|
}
|
|
|
|
void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) {
|
|
// determine the UART to use
|
|
int was_masked;
|
|
|
|
serial_flow_irq_set(obj, 0);
|
|
|
|
if (type == FlowControlRTSCTS) {
|
|
#if defined ( __ICCARM__ )
|
|
was_masked = __disable_irq_iar();
|
|
#else
|
|
was_masked = __disable_irq();
|
|
#endif /* __ICCARM__ */
|
|
obj->uart->SCFCR = 0x0008u; // CTS/RTS enable
|
|
if (!was_masked) {
|
|
__enable_irq();
|
|
}
|
|
pinmap_pinout(rxflow, PinMap_UART_RTS);
|
|
pinmap_pinout(txflow, PinMap_UART_CTS);
|
|
} else {
|
|
#if defined ( __ICCARM__ )
|
|
was_masked = __disable_irq_iar();
|
|
#else
|
|
was_masked = __disable_irq();
|
|
#endif /* __ICCARM__ */
|
|
obj->uart->SCFCR = 0x0000u; // CTS/RTS diable
|
|
if (!was_masked) {
|
|
__enable_irq();
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
|
|
|