mirror of https://github.com/ARMmbed/mbed-os.git
91 lines
3.4 KiB
C
91 lines
3.4 KiB
C
/*
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* Copyright (c) 2019, Nuvoton Technology Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "analogin_api.h"
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void mbed_sdk_init(void)
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{
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// NOTE: Support singleton semantics to be called from other init functions
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static int inited = 0;
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if (inited) {
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return;
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}
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inited = 1;
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/*---------------------------------------------------------------------------------------------------------*/
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/* Init System Clock */
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/*---------------------------------------------------------------------------------------------------------*/
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/* Unlock protected registers */
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SYS_UnlockReg();
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#if defined(NU_HXT_ENABLE) && (NU_HXT_ENABLE == 1UL)
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/* HXT Enable: Set XT1_OUT(PF.2) and XT1_IN(PF.3) to input mode */
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PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk);
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#endif
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/* LXT Enable: Set X32_OUT(PF.4) and X32_IN(PF.5) to input mode */
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PF->MODE &= ~(GPIO_MODE_MODE4_Msk | GPIO_MODE_MODE5_Msk);
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/* Enable HIRC clock (Internal RC 48MHz) */
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CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
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#if defined(NU_HXT_ENABLE) && (NU_HXT_ENABLE == 1UL)
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/* Enable HXT clock (external XTAL 12MHz) */
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CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
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#endif
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/* Enable LIRC for lp_ticker */
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CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk);
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/* Enable LXT for RTC */
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CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk);
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/* Wait for HIRC clock ready */
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CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
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#if defined(NU_HXT_ENABLE) && (NU_HXT_ENABLE == 1UL)
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/* Wait for HXT clock ready */
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CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
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#endif
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/* Wait for LIRC clock ready */
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CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
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/* Wait for LXT clock ready */
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CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk);
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#if defined(NU_HXT_ENABLE) && (NU_HXT_ENABLE == 1UL)
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/* HXT Enable: Disable digital input path of analog pin XT1_OUT to prevent leakage */
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GPIO_DISABLE_DIGITAL_PATH(PF, (1ul << 2));
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/* HXT Enable: Disable digital input path of analog pin XT1_IN to prevent leakage */
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GPIO_DISABLE_DIGITAL_PATH(PF, (1ul << 3));
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#endif
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/* LXT Enable: Disable digital input path of analog pin X32_OUT to prevent leakage */
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GPIO_DISABLE_DIGITAL_PATH(PF, (1ul << 4));
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/* LXT Enable: Disable digital input path of analog pin XT32_IN to prevent leakage */
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GPIO_DISABLE_DIGITAL_PATH(PF, (1ul << 5));
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/* Select HCLK clock source as HIRC and HCLK clock divider as 1 */
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CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
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/* Set both PCLK0 and PCLK1 as HCLK/2 */
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CLK->PCLKDIV = CLK_PCLKDIV_APB0DIV_DIV2 | CLK_PCLKDIV_APB1DIV_DIV2;
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/* Update System Core Clock */
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/* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
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SystemCoreClockUpdate();
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/* Lock protected registers */
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SYS_LockReg();
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}
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