Some low power tickers take multiple cycles of the low power clock
to set a compare value. Because of this if the compare value is set
twice back-to-back these implementations will block until that time
has passed. This can cause system stability issues since interrupts
are disabling for this time.
To gracefully support this kind of hardware this patch adds code
to prevent back-to-back writes to the hardware. It does this by
recording the low power clock cycle of the initial write. If any
writes come in too soon after this initial write the microsecond
ticker is used to schedule the new write in the future when the
hardware is ready to accept a new value.
To enable this feature on a target the macro LOWPOWERTIMER_DELAY_TICKS
must be set to the number of low power clock cycles that must elapse
between writes to the low power timer.
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