mirror of https://github.com/ARMmbed/mbed-os.git
290 lines
11 KiB
C
290 lines
11 KiB
C
/* Copyright (c) 2017 mbed.org, MIT License
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
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* and associated documentation files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all copies or
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* substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
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* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef USBHALHOST_STM_H
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#define USBHALHOST_STM_H
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#if defined(TARGET_DISCO_F746NG)
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#if (MBED_CONF_TARGET_USB_SPEED == 1) // Defined in json configuration file
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#define TARGET_DISCO_F746NG_HS
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#else
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#define TARGET_DISCO_F746NG_FS
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#endif
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#endif
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#if defined(TARGET_DISCO_F746NG_HS) || defined(TARGET_DISCO_F769NI)
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#define USBHAL_IRQn OTG_HS_IRQn
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#else
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#define USBHAL_IRQn OTG_FS_IRQn
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#endif
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#define HCCA_SIZE sizeof(HCD_HandleTypeDef)
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#define ED_SIZE sizeof(HCED)
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#define TD_SIZE sizeof(HCTD)
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#define TOTAL_SIZE (HCCA_SIZE + (MAX_ENDPOINT * ED_SIZE) + (MAX_TD * TD_SIZE))
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/* STM device FS have 11 channels (definition is for 60 channels) */
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static volatile uint8_t usb_buf[TOTAL_SIZE];
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typedef struct {
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/* store the request ongoing on each endpoit */
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/* 1st field of structure avoid giving knowledge of all structure to
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* endpoint */
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volatile uint32_t addr[MAX_ENDPOINT];
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USBHALHost *inst;
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void (USBHALHost::*deviceConnected)(int hub, int port, bool lowSpeed, USBHostHub * hub_parent);
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void (USBHALHost::*deviceDisconnected)(int hub, int port, USBHostHub * hub_parent, volatile uint32_t addr);
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void (USBHALHost::*transferCompleted)(volatile uint32_t addr);
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} USBHALHost_Private_t;
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static gpio_t gpio_powerpin;
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// NUCLEO_64 boards
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#if defined(TARGET_NUCLEO_F401RE) || \
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defined(TARGET_NUCLEO_F411RE) || \
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defined(TARGET_NUCLEO_F446RE) || \
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defined(TARGET_NUCLEO_L476RG) || \
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defined(TARGET_NUCLEO_L486RG)
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#define USB_POWER_ON 0
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#define USB_POWER_OFF 1
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#define USB_POWERPIN_CONFIG {__HAL_RCC_GPIOC_CLK_ENABLE();gpio_init_out_ex(&gpio_powerpin, PC_0, USB_POWER_OFF);}
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// NUCLEO_144 boards
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#elif defined(TARGET_NUCLEO_F207ZG) || \
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defined(TARGET_NUCLEO_F412ZG) || \
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defined(TARGET_NUCLEO_F413ZH) || \
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defined(TARGET_NUCLEO_F429ZI) || \
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defined(TARGET_NUCLEO_F439ZI) || \
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defined(TARGET_NUCLEO_F446ZE) || \
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defined(TARGET_NUCLEO_F767ZI) || \
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defined(TARGET_NUCLEO_F746ZG) || \
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defined(TARGET_NUCLEO_F756ZG) || \
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defined(TARGET_NUCLEO_F767ZI)
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#define USB_POWER_ON 1
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#define USB_POWER_OFF 0
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#define USB_POWERPIN_CONFIG {__HAL_RCC_GPIOG_CLK_ENABLE();gpio_init_out_ex(&gpio_powerpin, PG_6, USB_POWER_OFF);}
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// DISCOVERY boards
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#elif defined(TARGET_DISCO_F413ZH)
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#define USB_POWER_ON 0
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#define USB_POWER_OFF 1
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#define USB_POWERPIN_CONFIG {__HAL_RCC_GPIOG_CLK_ENABLE();gpio_init_out_ex(&gpio_powerpin, PG_8, USB_POWER_OFF);}
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#elif defined(TARGET_DISCO_F469NI)
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#define USB_POWER_ON 1
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#define USB_POWER_OFF 0
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#define USB_POWERPIN_CONFIG {__HAL_RCC_GPIOB_CLK_ENABLE();gpio_init_out_ex(&gpio_powerpin, PB_2, USB_POWER_OFF);}
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#elif defined(TARGET_DISCO_F746NG_FS)
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#define USB_POWER_ON 0
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#define USB_POWER_OFF 1
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#define USB_POWERPIN_CONFIG {__HAL_RCC_GPIOD_CLK_ENABLE();gpio_init_out_ex(&gpio_powerpin, PD_5, USB_POWER_OFF);}
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#elif defined(TARGET_DISCO_F746NG_HS)
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#define USB_POWER_ON 0
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#define USB_POWER_OFF 1
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#define USB_POWERPIN_CONFIG {}
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#elif defined(TARGET_DISCO_F769NI)
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#define USB_POWER_ON 0
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#define USB_POWER_OFF 1
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#define USB_POWERPIN_CONFIG {}
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#elif defined(TARGET_DISCO_L475VG_IOT01A)
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#define USB_POWER_ON 0
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#define USB_POWER_OFF 1
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#define USB_POWERPIN_CONFIG {__HAL_RCC_GPIOD_CLK_ENABLE();gpio_init_out_ex(&gpio_powerpin, PD_12, USB_POWER_OFF);}
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#elif defined(TARGET_DISCO_L476VG)
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#define USB_POWER_ON 0
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#define USB_POWER_OFF 1
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#define USB_POWERPIN_CONFIG {__HAL_RCC_GPIOC_CLK_ENABLE();gpio_init_out_ex(&gpio_powerpin, PC_9, USB_POWER_OFF);}
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#else
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#error "USB power pin is not configured !"
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#endif
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void usb_vbus( uint8_t state)
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{
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if (state == 0) {
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gpio_write(&gpio_powerpin, USB_POWER_OFF);
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} else {
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gpio_write(&gpio_powerpin, USB_POWER_ON);
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}
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wait(0.2);
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}
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USBHALHost::USBHALHost()
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{
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instHost = this;
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HCD_HandleTypeDef *hhcd = {0};
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USBHALHost_Private_t *HALPriv = new(USBHALHost_Private_t);
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memset(HALPriv, 0, sizeof(USBHALHost_Private_t));
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memInit();
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memset((void*)usb_hcca, 0, HCCA_SIZE);
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hhcd = (HCD_HandleTypeDef *)usb_hcca;
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hhcd->pData = (void*)HALPriv;
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#if defined(TARGET_DISCO_F746NG_HS) || defined(TARGET_DISCO_F769NI)
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hhcd->Instance = USB_OTG_HS;
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hhcd->Init.speed = HCD_SPEED_HIGH;
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hhcd->Init.phy_itface = HCD_PHY_ULPI;
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#else
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hhcd->Instance = USB_OTG_FS;
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hhcd->Init.speed = HCD_SPEED_FULL;
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hhcd->Init.phy_itface = HCD_PHY_EMBEDDED;
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#endif
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hhcd->Init.Host_channels = 11;
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hhcd->Init.dma_enable = 0; // for now failed with dma
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hhcd->Init.low_power_enable = 0;
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hhcd->Init.Sof_enable = 0;
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hhcd->Init.vbus_sensing_enable = 0;
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hhcd->Init.use_external_vbus = 1;
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hhcd->Init.lpm_enable = 0;
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HALPriv->inst = this;
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HALPriv->deviceConnected = &USBHALHost::deviceConnected;
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HALPriv->deviceDisconnected = &USBHALHost::deviceDisconnected;
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HALPriv->transferCompleted = &USBHALHost::transferCompleted;
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for (int i = 0; i < MAX_ENDPOINT; i++) {
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edBufAlloc[i] = false;
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HALPriv->addr[i] = (uint32_t)-1;
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}
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for (int i = 0; i < MAX_TD; i++) {
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tdBufAlloc[i] = false;
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}
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__HAL_RCC_PWR_CLK_ENABLE();
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#ifdef TARGET_STM32L4
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HAL_PWREx_EnableVddUSB();
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#endif
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// Configure USB pins
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#if defined(TARGET_NUCLEO_F401RE) || \
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defined(TARGET_NUCLEO_F411RE) || \
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defined(TARGET_NUCLEO_F446RE) || \
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defined(TARGET_NUCLEO_L476RG) || \
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defined(TARGET_NUCLEO_L486RG) || \
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defined(TARGET_NUCLEO_F207ZG) || \
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defined(TARGET_NUCLEO_F412ZG) || \
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defined(TARGET_NUCLEO_F413ZH) || \
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defined(TARGET_NUCLEO_F429ZI) || \
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defined(TARGET_NUCLEO_F439ZI) || \
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defined(TARGET_NUCLEO_F446ZE) || \
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defined(TARGET_NUCLEO_F767ZI) || \
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defined(TARGET_NUCLEO_F746ZG) || \
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defined(TARGET_NUCLEO_F756ZG) || \
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defined(TARGET_NUCLEO_F767ZI) || \
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defined(TARGET_DISCO_F413ZH) || \
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defined(TARGET_DISCO_F469NI) || \
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defined(TARGET_DISCO_L475VG_IOT01A)
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__HAL_RCC_GPIOA_CLK_ENABLE();
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pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // DM
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pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // DP
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pin_function(PA_10, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS)); // ID
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pin_function(PA_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // VBUS
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#elif defined(TARGET_DISCO_F746NG_FS)
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__HAL_RCC_GPIOA_CLK_ENABLE();
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pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // DM
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pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // DP
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pin_function(PA_10, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS)); // ID
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__HAL_RCC_GPIOJ_CLK_ENABLE();
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pin_function(PJ_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // VBUS
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#elif defined(TARGET_DISCO_F746NG_HS)
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__HAL_RCC_GPIOA_CLK_ENABLE();
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__HAL_RCC_GPIOB_CLK_ENABLE();
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__HAL_RCC_GPIOC_CLK_ENABLE();
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__HAL_RCC_GPIOH_CLK_ENABLE();
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pin_function(PA_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // CLK
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pin_function(PA_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D0
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pin_function(PB_0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D1
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pin_function(PB_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D2
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pin_function(PB_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D3
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pin_function(PB_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D4
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pin_function(PB_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D5
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pin_function(PB_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D6
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pin_function(PB_13, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D7
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pin_function(PC_0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // STP
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pin_function(PH_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // NXT
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pin_function(PC_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // DIR
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#elif defined(TARGET_DISCO_F769NI)
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__HAL_RCC_GPIOA_CLK_ENABLE();
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__HAL_RCC_GPIOB_CLK_ENABLE();
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__HAL_RCC_GPIOC_CLK_ENABLE();
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__HAL_RCC_GPIOH_CLK_ENABLE();
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__HAL_RCC_GPIOI_CLK_ENABLE();
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pin_function(PA_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // CLK
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pin_function(PA_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D0
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pin_function(PB_0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D1
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pin_function(PB_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D2
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pin_function(PB_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D3
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pin_function(PB_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D4
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pin_function(PB_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D5
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pin_function(PB_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D6
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pin_function(PB_13, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D7
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pin_function(PC_0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // STP
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pin_function(PH_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // NXT
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pin_function(PI_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // DIR
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#elif defined(TARGET_DISCO_L476VG)
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__HAL_RCC_GPIOA_CLK_ENABLE();
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pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // DM
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pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // DP
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pin_function(PA_10, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS)); // ID
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pin_function(PC_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // VBUS
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#elif defined(TARGET_STEVAL_3DP001V1)
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__HAL_RCC_GPIOA_CLK_ENABLE();
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pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // DM
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pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // DP
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#else
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#error "USB pins are not configured !"
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#endif
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// Configure USB POWER pin
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USB_POWERPIN_CONFIG;
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// Enable clocks
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__HAL_RCC_SYSCFG_CLK_ENABLE();
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#if defined(TARGET_DISCO_F746NG_HS) || defined(TARGET_DISCO_F769NI)
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__HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE();
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__HAL_RCC_USB_OTG_HS_CLK_ENABLE();
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#else
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__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
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#endif
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// Set USB interrupt
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HAL_NVIC_SetPriority(USBHAL_IRQn, 5, 0);
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NVIC_SetVector(USBHAL_IRQn, (uint32_t)&_usbisr);
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}
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#endif // USBHALHOST_STM_H
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