mirror of https://github.com/ARMmbed/mbed-os.git
1516 lines
39 KiB
C++
1516 lines
39 KiB
C++
<<<<<<< HEAD
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<<<<<<< HEAD
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/* mbed Microcontroller Library
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* Copyright (c) 2018 Gigadevice
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <stdlib.h>
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#include "cmsis_os.h"
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#include "mbed_interface.h"
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#include "mbed_assert.h"
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#include "mbed_shared_queues.h"
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#include "netsocket/nsapi_types.h"
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#include "gd32xx_emac.h"
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/* \brief Flags for worker thread */
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#define _ENET_FLAG_RX (1)
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/** \brief Driver thread priority */
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#define _THREAD_STACKSIZE (512)
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#define _THREAD_PRIORITY (osPriorityHigh)
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#define _PHY_TASK_PERIOD_MS (200)
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#define _ENET_HW_ADDR_SIZE (6)
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#define _ENET_MTU_SIZE (1500)
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#define _ENET_IF_NAME "gd"
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#define _ENET_BOARD_PHY_ADDRESS (0x01)
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#define _ENET_HARDWARE_CHECKSUM (0)
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#define _GD_MAC_ADDR0 0x02
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#define _GD_MAC_ADDR1 0xaa
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#define _GD_MAC_ADDR2 0xbb
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#define _GD32_ID_ADDR 0x1FFFF7E8
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/* ENET RxDMA/TxDMA descriptor */
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extern enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM], txdesc_tab[ENET_TXBUF_NUM];
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/* ENET receive buffer */
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extern uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE];
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/* ENET transmit buffer */
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extern uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE];
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/*global transmit and receive descriptors pointers */
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extern enet_descriptors_struct *dma_current_txdesc;
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extern enet_descriptors_struct *dma_current_rxdesc;
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#ifdef __cplusplus
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extern "C" {
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#endif
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void ENET_IRQHandler(void);
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void enet_bsp_init(void);
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#ifdef __cplusplus
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}
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#endif
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/**
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* Ethernet IRQ Handler
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*
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*/
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void ENET_IRQHandler(void)
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{
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/* frame received */
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if (SET == enet_interrupt_flag_get(ENET_DMA_INT_FLAG_RS)) {
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/* clear the enet DMA Rx interrupt pending bits */
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enet_interrupt_flag_clear(ENET_DMA_INT_FLAG_RS_CLR);
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enet_interrupt_flag_clear(ENET_DMA_INT_FLAG_NI_CLR);
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/* Ethernet Rx Transfer completed callback */
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GD32_EMAC &emac = GD32_EMAC::get_instance();
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if (emac.rx_thread) {
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osThreadFlagsSet(emac.rx_thread, _ENET_FLAG_RX);
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}
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}
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}
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GD32_EMAC::GD32_EMAC()
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: rx_thread(0),
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phy_status(0)
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{
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}
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static osThreadId_t create_new_thread(const char *threadName, void (*thread)(void *arg), void *arg, int stacksize, osPriority_t priority, mbed_rtos_storage_thread_t *thread_cb)
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{
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osThreadAttr_t attr = {0};
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attr.name = threadName;
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attr.stack_mem = malloc(stacksize);
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attr.cb_mem = thread_cb;
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attr.stack_size = stacksize;
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attr.cb_size = sizeof(mbed_rtos_storage_thread_t);
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attr.priority = priority;
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return osThreadNew(thread, arg, &attr);
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}
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/** \brief Low level init of the MAC and PHY.
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*
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*/
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bool GD32_EMAC::low_level_init()
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{
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/* Init ETH */
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uint8_t macaddr[6];
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uint32_t i;
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#if (MBED_MAC_ADDRESS_SUM != MBED_MAC_ADDR_INTERFACE)
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MACAddr[0] = MBED_MAC_ADDR_0;
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MACAddr[1] = MBED_MAC_ADDR_1;
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MACAddr[2] = MBED_MAC_ADDR_2;
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MACAddr[3] = MBED_MAC_ADDR_3;
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MACAddr[4] = MBED_MAC_ADDR_4;
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MACAddr[5] = MBED_MAC_ADDR_5;
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#else
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mbed_mac_address((char *)macaddr);
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#endif
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enet_bsp_init();
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/* reset ethernet on AHB bus */
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enet_deinit();
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if (ERROR == enet_software_reset()) {
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while (1);
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}
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#if (1 == _ENET_HARDWARE_CHECKSUM)
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if (ERROR == enet_init(ENET_AUTO_NEGOTIATION, ENET_AUTOCHECKSUM_DROP_FAILFRAMES, ENET_BROADCAST_FRAMES_PASS)) {
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while (1);
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}
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#else
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if (ERROR == enet_init(ENET_AUTO_NEGOTIATION, ENET_NO_AUTOCHECKSUM, ENET_BROADCAST_FRAMES_PASS)) {
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while (1);
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}
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#endif
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/* initialize MAC address in ethernet MAC */
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enet_mac_address_set(ENET_MAC_ADDRESS0, macaddr);
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enet_interrupt_enable(ENET_DMA_INT_NIE);
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enet_interrupt_enable(ENET_DMA_INT_RIE);
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/* Initialize Tx Descriptors list: Chain Mode */
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enet_descriptors_chain_init(ENET_DMA_TX);
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#if (1 == _ENET_HARDWARE_CHECKSUM)
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/* enable the TCP, UDP and ICMP checksum insertion for the Tx frames */
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for (i = 0; i < ENET_TXBUF_NUM; i++) {
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enet_transmit_checksum_config(&txdesc_tab[i], ENET_CHECKSUM_TCPUDPICMP_FULL);
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}
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#endif
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/* Initialize Rx Descriptors list: Chain Mode */
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enet_descriptors_chain_init(ENET_DMA_RX);
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/* enable ethernet Rx interrrupt */
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for (i = 0; i < ENET_RXBUF_NUM; i++) {
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enet_rx_desc_immediate_receive_complete_interrupt(&rxdesc_tab[i]);
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}
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/* enable MAC and DMA transmission and reception */
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enet_enable();
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return true;
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}
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/**
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* Sends the packet over the link
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*
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* That can not be called from an interrupt context.
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*
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* @param buf Packet to be send
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* @return True if the packet was send successfully, False otherwise
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*/
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bool GD32_EMAC::link_out(emac_mem_buf_t *buf)
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{
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emac_mem_buf_t *q;
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uint8_t *buffer;
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uint16_t framelength = 0;
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/* Get exclusive access */
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TXLockMutex.lock();
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while ((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)) {}
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/* copy frame from pbufs to driver buffers */
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buffer = reinterpret_cast<uint8_t *>(enet_desc_information_get(dma_current_txdesc, TXDESC_BUFFER_1_ADDR));
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for (q = buf; q != NULL; q = memory_manager->get_next(q)) {
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memcpy(static_cast<uint8_t *>(&buffer[framelength]), static_cast<uint8_t *>(memory_manager->get_ptr(q)), memory_manager->get_len(q));
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framelength = framelength + memory_manager->get_len(q);
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}
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/* Prepare transmit descriptors to give to DMA */
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if (SUCCESS != ENET_NOCOPY_FRAME_TRANSMIT(framelength)) {
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while (1);
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}
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memory_manager->free(buf);
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/* Restore access */
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TXLockMutex.unlock();
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return true;
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}
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/** \brief Attempt to read a packet from the EMAC interface.
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*
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*/
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emac_mem_buf_t *GD32_EMAC::low_level_input(void)
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{
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emac_mem_buf_t *p = NULL, *q;
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uint32_t l = 0;
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uint16_t len;
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uint8_t *buffer;
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/* obtain the size of the packet and put it into the "len" variable. */
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len = enet_desc_information_get(dma_current_rxdesc, RXDESC_FRAME_LENGTH);
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buffer = reinterpret_cast<uint8_t *>(enet_desc_information_get(dma_current_rxdesc, RXDESC_BUFFER_1_ADDR));
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if (len > 0) {
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/* Allocate a memory buffer chain from buffer pool */
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p = memory_manager->alloc_pool(len, 0);
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} else {
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return p;
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}
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if (p != NULL) {
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for (q = p; q != NULL; q = memory_manager->get_next(q)) {
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memcpy(static_cast<uint8_t *>(memory_manager->get_ptr(q)), static_cast<uint8_t *>(&buffer[l]), memory_manager->get_len(q));
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l = l + memory_manager->get_len(q);
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}
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}
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ENET_NOCOPY_FRAME_RECEIVE();
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return p;
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}
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/** \brief Attempt to read a packet from the EMAC interface.
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*
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*/
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void GD32_EMAC::packet_rx()
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{
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/* move received packet into a new buf */
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while (1) {
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emac_mem_buf_t *p = NULL;
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p = low_level_input();
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if (p) {
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emac_link_input_cb(p);
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} else {
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break;
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}
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}
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}
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/** \brief Worker thread.
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*
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* Woken by thread flags to receive packets or clean up transmit
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*
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* \param[in] pvParameters pointer to the interface data
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*/
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void GD32_EMAC::thread_function(void *pvParameters)
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{
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static struct GD32_EMAC *gd32_enet = static_cast<GD32_EMAC *>(pvParameters);
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while (1) {
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uint32_t flags = osThreadFlagsWait(_ENET_FLAG_RX, osFlagsWaitAny, osWaitForever);
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if (flags & _ENET_FLAG_RX) {
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gd32_enet->packet_rx();
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}
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}
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}
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/**
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* This task checks phy link status and updates net status
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*/
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void GD32_EMAC::phy_task()
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{
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uint16_t regval;
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enet_phy_write_read(ENET_PHY_READ, _ENET_BOARD_PHY_ADDRESS, PHY_REG_BSR, ®val);
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if (emac_link_state_cb) {
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regval &= PHY_LINKED_STATUS;
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if (phy_status != regval) {
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if (regval == PHY_LINKED_STATUS) {
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emac_link_state_cb(true);;
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} else {
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emac_link_state_cb(false);
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}
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}
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}
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phy_status = regval;
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}
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void GD32_EMAC::eth_arch_enable_interrupts(void)
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{
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nvic_irq_enable(ENET_IRQn, 7, 0);
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}
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void GD32_EMAC::eth_arch_disable_interrupts(void)
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{
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nvic_irq_disable(ENET_IRQn);
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}
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/** This returns a unique 6-byte MAC address, based on the device UID
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* This function overrides hal/common/mbed_interface.c function
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* @param mac A 6-byte array to write the MAC address
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*/
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void mbed_mac_address(char *mac)
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{
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uint32_t unique_id;
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unique_id = *(uint32_t *)_GD32_ID_ADDR;
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mac[0] = _GD_MAC_ADDR0;
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mac[1] = _GD_MAC_ADDR1;
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mac[2] = _GD_MAC_ADDR2;
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mac[3] = (unique_id & 0x00ff0000) >> 16;
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mac[4] = (unique_id & 0x0000ff00) >> 8;
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mac[5] = (unique_id & 0x000000ff);
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}
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/**
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* Initializes the HW
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*
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* @return True on success, False in case of an error.
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*/
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bool GD32_EMAC::power_up()
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{
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/* Initialize the hardware */
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if (true != low_level_init()) {
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return false;
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}
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/* Worker thread */
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rx_thread = create_new_thread("gd32_emac_thread", &GD32_EMAC::thread_function, this, _THREAD_STACKSIZE, _THREAD_PRIORITY, &rx_thread_cb);
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phy_task_handle = mbed::mbed_event_queue()->call_every(_PHY_TASK_PERIOD_MS, mbed::callback(this, &GD32_EMAC::phy_task));
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/* Allow the PHY task to detect the initial link state and set up the proper flags */
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osDelay(10);
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eth_arch_enable_interrupts();
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return true;
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}
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/**
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* Return maximum transmission unit
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*
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* @return MTU in bytes
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*/
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uint32_t GD32_EMAC::get_mtu_size() const
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{
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return _ENET_MTU_SIZE;
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}
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/**
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* Gets memory buffer alignment preference
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*
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* Gets preferred memory buffer alignment of the Emac device. IP stack may or may not
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* align link out memory buffer chains using the alignment.
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*
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* @return Memory alignment requirement in bytes
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*/
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uint32_t GD32_EMAC::get_align_preference() const
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{
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return 0;
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}
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/**
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* Return interface name
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*
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* @param name Pointer to where the name should be written
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* @param size Maximum number of character to copy
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*/
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void GD32_EMAC::get_ifname(char *name, uint8_t size) const
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{
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memcpy(name, _ENET_IF_NAME, (size < sizeof(_ENET_IF_NAME)) ? size : sizeof(_ENET_IF_NAME));
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}
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/**
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* Returns size of the underlying interface HW address size.
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*
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* @return HW address size in bytes
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*/
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uint8_t GD32_EMAC::get_hwaddr_size() const
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{
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return _ENET_HW_ADDR_SIZE;
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}
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/**
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* Returns size of the underlying interface HW address size.
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*
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* @return HW address size in bytes
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*/
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bool GD32_EMAC::get_hwaddr(uint8_t *addr) const
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{
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mbed_mac_address((char *)addr);
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return true;
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}
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/**
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* Set HW address for interface
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*
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* Provided address has to be of correct size, see @a get_hwaddr_size
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*
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* Called to set the MAC address to actually use - if @a get_hwaddr is provided
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* the stack would normally use that, but it could be overridden, eg for test
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* purposes.
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*
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* @param addr Address to be set
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*/
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void GD32_EMAC::set_hwaddr(const uint8_t *addr)
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{
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/* No-op at this stage */
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}
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/**
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* Sets a callback that needs to be called for packets received for that interface
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*
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* @param input_cb Function to be register as a callback
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*/
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void GD32_EMAC::set_link_input_cb(emac_link_input_cb_t input_cb)
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{
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emac_link_input_cb = input_cb;
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}
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/**
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* Sets a callback that needs to be called on link status changes for given interface
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*
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* @param state_cb Function to be register as a callback
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*/
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void GD32_EMAC::set_link_state_cb(emac_link_state_change_cb_t state_cb)
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{
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emac_link_state_cb = state_cb;
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}
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/** Add device to a multicast group
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*
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* @param address A multicast group hardware address
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*/
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void GD32_EMAC::add_multicast_group(const uint8_t *addr)
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{
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/* No-op at this stage */
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}
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/** Remove device from a multicast group
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*
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* @param address A multicast group hardware address
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*/
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void GD32_EMAC::remove_multicast_group(const uint8_t *addr)
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{
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/* No-op at this stage */
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}
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/** Request reception of all multicast packets
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*
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* @param all True to receive all multicasts
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* False to receive only multicasts addressed to specified groups
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*/
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void GD32_EMAC::set_all_multicast(bool all)
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{
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/* No-op at this stage */
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}
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/**
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* Deinitializes the HW
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*
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*/
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void GD32_EMAC::power_down()
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{
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/* No-op at this stage */
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}
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/** Sets memory manager that is used to handle memory buffers
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*
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* @param mem_mngr Pointer to memory manager
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*/
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void GD32_EMAC::set_memory_manager(EMACMemoryManager &mem_mngr)
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{
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memory_manager = &mem_mngr;
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}
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GD32_EMAC &GD32_EMAC::get_instance()
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{
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static GD32_EMAC emac;
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return emac;
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}
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/* Weak so a module can override */
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MBED_WEAK EMAC &EMAC::get_default_instance()
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{
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return GD32_EMAC::get_instance();
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}
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=======
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/* mbed Microcontroller Library
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* Copyright (c) 2018 Gigadevice Semiconductor Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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|
* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <stdlib.h>
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#include "cmsis_os.h"
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#include "mbed_interface.h"
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#include "mbed_assert.h"
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#include "mbed_shared_queues.h"
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#include "netsocket/nsapi_types.h"
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#include "gd32xx_emac.h"
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/* \brief Flags for worker thread */
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#define _ENET_FLAG_RX (1)
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/** \brief Driver thread priority */
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#define _THREAD_STACKSIZE (512)
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#define _THREAD_PRIORITY (osPriorityHigh)
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#define _PHY_TASK_PERIOD_MS (200)
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#define _ENET_HW_ADDR_SIZE (6)
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#define _ENET_MTU_SIZE (1500)
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#define _ENET_IF_NAME "gd"
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#define _ENET_BOARD_PHY_ADDRESS (0x01)
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#define _ENET_HARDWARE_CHECKSUM (0)
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#define _GD_MAC_ADDR0 0x02
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#define _GD_MAC_ADDR1 0xaa
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#define _GD_MAC_ADDR2 0xbb
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#define _GD32_ID_ADDR 0x1FFFF7E8
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/* ENET RxDMA/TxDMA descriptor */
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extern enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM], txdesc_tab[ENET_TXBUF_NUM];
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/* ENET receive buffer */
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extern uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE];
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/* ENET transmit buffer */
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extern uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE];
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/*global transmit and receive descriptors pointers */
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extern enet_descriptors_struct *dma_current_txdesc;
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extern enet_descriptors_struct *dma_current_rxdesc;
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#ifdef __cplusplus
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extern "C" {
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#endif
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void ENET_IRQHandler(void);
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void enet_bsp_init(void);
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#ifdef __cplusplus
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}
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#endif
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/**
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* Ethernet IRQ Handler
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*
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*/
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void ENET_IRQHandler(void)
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{
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/* frame received */
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if (SET == enet_interrupt_flag_get(ENET_DMA_INT_FLAG_RS)) {
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/* clear the enet DMA Rx interrupt pending bits */
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enet_interrupt_flag_clear(ENET_DMA_INT_FLAG_RS_CLR);
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enet_interrupt_flag_clear(ENET_DMA_INT_FLAG_NI_CLR);
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/* Ethernet Rx Transfer completed callback */
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GD32_EMAC &emac = GD32_EMAC::get_instance();
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if (emac.rx_thread) {
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osThreadFlagsSet(emac.rx_thread, _ENET_FLAG_RX);
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}
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}
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}
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GD32_EMAC::GD32_EMAC()
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: rx_thread(0),
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phy_status(0)
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{
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}
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static osThreadId_t create_new_thread(const char *threadName, void (*thread)(void *arg), void *arg, int stacksize, osPriority_t priority, mbed_rtos_storage_thread_t *thread_cb)
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{
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osThreadAttr_t attr = {0};
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attr.name = threadName;
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attr.stack_mem = malloc(stacksize);
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attr.cb_mem = thread_cb;
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attr.stack_size = stacksize;
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attr.cb_size = sizeof(mbed_rtos_storage_thread_t);
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attr.priority = priority;
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return osThreadNew(thread, arg, &attr);
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}
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/** \brief Low level init of the MAC and PHY.
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*
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*/
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bool GD32_EMAC::low_level_init()
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{
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/* Init ETH */
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uint8_t macaddr[6];
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uint32_t i;
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#if (MBED_MAC_ADDRESS_SUM != MBED_MAC_ADDR_INTERFACE)
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MACAddr[0] = MBED_MAC_ADDR_0;
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MACAddr[1] = MBED_MAC_ADDR_1;
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MACAddr[2] = MBED_MAC_ADDR_2;
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MACAddr[3] = MBED_MAC_ADDR_3;
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MACAddr[4] = MBED_MAC_ADDR_4;
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MACAddr[5] = MBED_MAC_ADDR_5;
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#else
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mbed_mac_address((char *)macaddr);
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#endif
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enet_bsp_init();
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/* reset ethernet on AHB bus */
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enet_deinit();
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if (ERROR == enet_software_reset()) {
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while (1);
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}
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#if (1 == _ENET_HARDWARE_CHECKSUM)
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if (ERROR == enet_init(ENET_AUTO_NEGOTIATION, ENET_AUTOCHECKSUM_DROP_FAILFRAMES, ENET_BROADCAST_FRAMES_PASS)) {
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while (1);
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}
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#else
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if (ERROR == enet_init(ENET_AUTO_NEGOTIATION, ENET_NO_AUTOCHECKSUM, ENET_BROADCAST_FRAMES_PASS)) {
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while (1);
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}
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#endif
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/* initialize MAC address in ethernet MAC */
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enet_mac_address_set(ENET_MAC_ADDRESS0, macaddr);
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enet_interrupt_enable(ENET_DMA_INT_NIE);
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enet_interrupt_enable(ENET_DMA_INT_RIE);
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/* Initialize Tx Descriptors list: Chain Mode */
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enet_descriptors_chain_init(ENET_DMA_TX);
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#if (1 == _ENET_HARDWARE_CHECKSUM)
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/* enable the TCP, UDP and ICMP checksum insertion for the Tx frames */
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for (i = 0; i < ENET_TXBUF_NUM; i++) {
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enet_transmit_checksum_config(&txdesc_tab[i], ENET_CHECKSUM_TCPUDPICMP_FULL);
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}
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#endif
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/* Initialize Rx Descriptors list: Chain Mode */
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enet_descriptors_chain_init(ENET_DMA_RX);
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/* enable ethernet Rx interrrupt */
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for (i = 0; i < ENET_RXBUF_NUM; i++) {
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enet_rx_desc_immediate_receive_complete_interrupt(&rxdesc_tab[i]);
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}
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/* enable MAC and DMA transmission and reception */
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enet_enable();
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return true;
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}
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/**
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* Sends the packet over the link
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*
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* That can not be called from an interrupt context.
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*
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* @param buf Packet to be send
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* @return True if the packet was send successfully, False otherwise
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*/
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bool GD32_EMAC::link_out(emac_mem_buf_t *buf)
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{
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emac_mem_buf_t *q;
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uint8_t *buffer;
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uint16_t framelength = 0;
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/* Get exclusive access */
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TXLockMutex.lock();
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while ((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)) {}
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/* copy frame from pbufs to driver buffers */
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buffer = reinterpret_cast<uint8_t *>(enet_desc_information_get(dma_current_txdesc, TXDESC_BUFFER_1_ADDR));
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for (q = buf; q != NULL; q = memory_manager->get_next(q)) {
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memcpy(static_cast<uint8_t *>(&buffer[framelength]), static_cast<uint8_t *>(memory_manager->get_ptr(q)), memory_manager->get_len(q));
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framelength = framelength + memory_manager->get_len(q);
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}
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/* Prepare transmit descriptors to give to DMA */
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if (SUCCESS != ENET_NOCOPY_FRAME_TRANSMIT(framelength)) {
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while (1);
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}
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memory_manager->free(buf);
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/* Restore access */
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TXLockMutex.unlock();
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return true;
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}
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/** \brief Attempt to read a packet from the EMAC interface.
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*
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*/
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emac_mem_buf_t *GD32_EMAC::low_level_input(void)
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{
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emac_mem_buf_t *p = NULL, *q;
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uint32_t l = 0;
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uint16_t len;
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uint8_t *buffer;
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/* obtain the size of the packet and put it into the "len" variable. */
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len = enet_desc_information_get(dma_current_rxdesc, RXDESC_FRAME_LENGTH);
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buffer = reinterpret_cast<uint8_t *>(enet_desc_information_get(dma_current_rxdesc, RXDESC_BUFFER_1_ADDR));
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if (len > 0) {
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/* Allocate a memory buffer chain from buffer pool */
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p = memory_manager->alloc_pool(len, 0);
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} else {
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return p;
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}
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if (p != NULL) {
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for (q = p; q != NULL; q = memory_manager->get_next(q)) {
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memcpy(static_cast<uint8_t *>(memory_manager->get_ptr(q)), static_cast<uint8_t *>(&buffer[l]), memory_manager->get_len(q));
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l = l + memory_manager->get_len(q);
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}
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}
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ENET_NOCOPY_FRAME_RECEIVE();
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return p;
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}
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/** \brief Attempt to read a packet from the EMAC interface.
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*
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*/
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void GD32_EMAC::packet_rx()
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{
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/* move received packet into a new buf */
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while (1) {
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emac_mem_buf_t *p = NULL;
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p = low_level_input();
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if (p) {
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emac_link_input_cb(p);
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} else {
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break;
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}
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}
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}
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/** \brief Worker thread.
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*
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* Woken by thread flags to receive packets or clean up transmit
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*
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* \param[in] pvParameters pointer to the interface data
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*/
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void GD32_EMAC::thread_function(void *pvParameters)
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{
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static struct GD32_EMAC *gd32_enet = static_cast<GD32_EMAC *>(pvParameters);
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while (1) {
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uint32_t flags = osThreadFlagsWait(_ENET_FLAG_RX, osFlagsWaitAny, osWaitForever);
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if (flags & _ENET_FLAG_RX) {
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gd32_enet->packet_rx();
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}
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}
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}
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/**
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* This task checks phy link status and updates net status
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*/
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void GD32_EMAC::phy_task()
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{
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uint16_t regval;
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enet_phy_write_read(ENET_PHY_READ, _ENET_BOARD_PHY_ADDRESS, PHY_REG_BSR, ®val);
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if (emac_link_state_cb) {
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regval &= PHY_LINKED_STATUS;
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if (phy_status != regval) {
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if (regval == PHY_LINKED_STATUS) {
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emac_link_state_cb(true);;
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} else {
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emac_link_state_cb(false);
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}
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}
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}
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phy_status = regval;
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}
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void GD32_EMAC::eth_arch_enable_interrupts(void)
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{
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nvic_irq_enable(ENET_IRQn, 7, 0);
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}
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void GD32_EMAC::eth_arch_disable_interrupts(void)
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{
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nvic_irq_disable(ENET_IRQn);
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}
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/** This returns a unique 6-byte MAC address, based on the device UID
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* This function overrides hal/common/mbed_interface.c function
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* @param mac A 6-byte array to write the MAC address
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*/
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void mbed_mac_address(char *mac)
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{
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uint32_t unique_id;
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unique_id = *(uint32_t *)_GD32_ID_ADDR;
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mac[0] = _GD_MAC_ADDR0;
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mac[1] = _GD_MAC_ADDR1;
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mac[2] = _GD_MAC_ADDR2;
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mac[3] = (unique_id & 0x00ff0000) >> 16;
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mac[4] = (unique_id & 0x0000ff00) >> 8;
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mac[5] = (unique_id & 0x000000ff);
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}
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/**
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* Initializes the HW
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*
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* @return True on success, False in case of an error.
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*/
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bool GD32_EMAC::power_up()
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{
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/* Initialize the hardware */
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if (true != low_level_init()) {
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return false;
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}
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/* Worker thread */
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rx_thread = create_new_thread("gd32_emac_thread", &GD32_EMAC::thread_function, this, _THREAD_STACKSIZE, _THREAD_PRIORITY, &rx_thread_cb);
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phy_task_handle = mbed::mbed_event_queue()->call_every(_PHY_TASK_PERIOD_MS, mbed::callback(this, &GD32_EMAC::phy_task));
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/* Allow the PHY task to detect the initial link state and set up the proper flags */
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osDelay(10);
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eth_arch_enable_interrupts();
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return true;
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}
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/**
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* Return maximum transmission unit
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*
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* @return MTU in bytes
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*/
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uint32_t GD32_EMAC::get_mtu_size() const
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{
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return _ENET_MTU_SIZE;
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}
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/**
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* Gets memory buffer alignment preference
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*
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* Gets preferred memory buffer alignment of the Emac device. IP stack may or may not
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* align link out memory buffer chains using the alignment.
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*
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* @return Memory alignment requirement in bytes
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*/
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uint32_t GD32_EMAC::get_align_preference() const
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{
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return 0;
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}
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/**
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* Return interface name
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*
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* @param name Pointer to where the name should be written
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* @param size Maximum number of character to copy
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*/
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void GD32_EMAC::get_ifname(char *name, uint8_t size) const
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{
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memcpy(name, _ENET_IF_NAME, (size < sizeof(_ENET_IF_NAME)) ? size : sizeof(_ENET_IF_NAME));
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}
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/**
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* Returns size of the underlying interface HW address size.
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*
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* @return HW address size in bytes
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*/
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uint8_t GD32_EMAC::get_hwaddr_size() const
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{
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return _ENET_HW_ADDR_SIZE;
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}
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/**
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* Returns size of the underlying interface HW address size.
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*
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* @return HW address size in bytes
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*/
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bool GD32_EMAC::get_hwaddr(uint8_t *addr) const
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{
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mbed_mac_address((char *)addr);
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return true;
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}
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/**
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* Set HW address for interface
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*
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* Provided address has to be of correct size, see @a get_hwaddr_size
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*
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* Called to set the MAC address to actually use - if @a get_hwaddr is provided
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* the stack would normally use that, but it could be overridden, eg for test
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* purposes.
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*
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* @param addr Address to be set
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*/
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void GD32_EMAC::set_hwaddr(const uint8_t *addr)
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{
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/* No-op at this stage */
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}
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/**
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* Sets a callback that needs to be called for packets received for that interface
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*
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* @param input_cb Function to be register as a callback
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*/
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void GD32_EMAC::set_link_input_cb(emac_link_input_cb_t input_cb)
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{
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emac_link_input_cb = input_cb;
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}
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/**
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* Sets a callback that needs to be called on link status changes for given interface
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*
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* @param state_cb Function to be register as a callback
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*/
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void GD32_EMAC::set_link_state_cb(emac_link_state_change_cb_t state_cb)
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{
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emac_link_state_cb = state_cb;
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}
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|
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/** Add device to a multicast group
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*
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* @param address A multicast group hardware address
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*/
|
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void GD32_EMAC::add_multicast_group(const uint8_t *addr)
|
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{
|
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/* No-op at this stage */
|
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}
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|
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/** Remove device from a multicast group
|
|
*
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* @param address A multicast group hardware address
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*/
|
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void GD32_EMAC::remove_multicast_group(const uint8_t *addr)
|
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{
|
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/* No-op at this stage */
|
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}
|
|
|
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/** Request reception of all multicast packets
|
|
*
|
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* @param all True to receive all multicasts
|
|
* False to receive only multicasts addressed to specified groups
|
|
*/
|
|
void GD32_EMAC::set_all_multicast(bool all)
|
|
{
|
|
/* No-op at this stage */
|
|
}
|
|
|
|
/**
|
|
* Deinitializes the HW
|
|
*
|
|
*/
|
|
void GD32_EMAC::power_down()
|
|
{
|
|
/* No-op at this stage */
|
|
}
|
|
|
|
/** Sets memory manager that is used to handle memory buffers
|
|
*
|
|
* @param mem_mngr Pointer to memory manager
|
|
*/
|
|
void GD32_EMAC::set_memory_manager(EMACMemoryManager &mem_mngr)
|
|
{
|
|
memory_manager = &mem_mngr;
|
|
}
|
|
|
|
GD32_EMAC &GD32_EMAC::get_instance()
|
|
{
|
|
static GD32_EMAC emac;
|
|
return emac;
|
|
}
|
|
|
|
/* Weak so a module can override */
|
|
MBED_WEAK EMAC &EMAC::get_default_instance()
|
|
{
|
|
return GD32_EMAC::get_instance();
|
|
}
|
|
>>>>>>> Update licence
|
|
=======
|
|
/* mbed Microcontroller Library
|
|
* Copyright (c) 2018 Gigadevice Semiconductor Inc.
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* http://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*/
|
|
|
|
#include <stdlib.h>
|
|
|
|
#include "cmsis_os.h"
|
|
|
|
#include "mbed_interface.h"
|
|
#include "mbed_assert.h"
|
|
#include "mbed_shared_queues.h"
|
|
#include "netsocket/nsapi_types.h"
|
|
|
|
#include "gd32xx_emac.h"
|
|
|
|
/* \brief Flags for worker thread */
|
|
#define _ENET_FLAG_RX (1)
|
|
|
|
/** \brief Driver thread priority */
|
|
#define _THREAD_STACKSIZE (512)
|
|
#define _THREAD_PRIORITY (osPriorityHigh)
|
|
|
|
#define _PHY_TASK_PERIOD_MS (200)
|
|
|
|
#define _ENET_HW_ADDR_SIZE (6)
|
|
#define _ENET_MTU_SIZE (1500)
|
|
#define _ENET_IF_NAME "gd"
|
|
|
|
#define _ENET_BOARD_PHY_ADDRESS (0x01)
|
|
#define _ENET_HARDWARE_CHECKSUM (0)
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#define _GD_MAC_ADDR0 0x02
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#define _GD_MAC_ADDR1 0xaa
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#define _GD_MAC_ADDR2 0xbb
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#define _GD32_ID_ADDR 0x1FFFF7E8
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/* ENET RxDMA/TxDMA descriptor */
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extern enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM], txdesc_tab[ENET_TXBUF_NUM];
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/* ENET receive buffer */
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extern uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE];
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/* ENET transmit buffer */
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extern uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE];
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/*global transmit and receive descriptors pointers */
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extern enet_descriptors_struct *dma_current_txdesc;
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extern enet_descriptors_struct *dma_current_rxdesc;
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#ifdef __cplusplus
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extern "C" {
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#endif
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void ENET_IRQHandler(void);
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void enet_bsp_init(void);
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#ifdef __cplusplus
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}
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#endif
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/**
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* Ethernet IRQ Handler
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*
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*/
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void ENET_IRQHandler(void)
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{
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/* frame received */
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if (SET == enet_interrupt_flag_get(ENET_DMA_INT_FLAG_RS)) {
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/* clear the enet DMA Rx interrupt pending bits */
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enet_interrupt_flag_clear(ENET_DMA_INT_FLAG_RS_CLR);
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enet_interrupt_flag_clear(ENET_DMA_INT_FLAG_NI_CLR);
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/* Ethernet Rx Transfer completed callback */
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GD32_EMAC &emac = GD32_EMAC::get_instance();
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if (emac.rx_thread) {
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osThreadFlagsSet(emac.rx_thread, _ENET_FLAG_RX);
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}
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}
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}
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GD32_EMAC::GD32_EMAC()
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: rx_thread(0),
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phy_status(0)
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{
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}
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static osThreadId_t create_new_thread(const char *threadName, void (*thread)(void *arg), void *arg, int stacksize, osPriority_t priority, mbed_rtos_storage_thread_t *thread_cb)
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{
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osThreadAttr_t attr = {0};
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attr.name = threadName;
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attr.stack_mem = malloc(stacksize);
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attr.cb_mem = thread_cb;
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attr.stack_size = stacksize;
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attr.cb_size = sizeof(mbed_rtos_storage_thread_t);
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attr.priority = priority;
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return osThreadNew(thread, arg, &attr);
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}
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/** \brief Low level init of the MAC and PHY.
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*
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*/
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bool GD32_EMAC::low_level_init()
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{
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/* Init ETH */
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uint8_t macaddr[6];
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uint32_t i;
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#if (MBED_MAC_ADDRESS_SUM != MBED_MAC_ADDR_INTERFACE)
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MACAddr[0] = MBED_MAC_ADDR_0;
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MACAddr[1] = MBED_MAC_ADDR_1;
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MACAddr[2] = MBED_MAC_ADDR_2;
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MACAddr[3] = MBED_MAC_ADDR_3;
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MACAddr[4] = MBED_MAC_ADDR_4;
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MACAddr[5] = MBED_MAC_ADDR_5;
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#else
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mbed_mac_address((char *)macaddr);
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#endif
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enet_bsp_init();
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/* reset ethernet on AHB bus */
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enet_deinit();
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if (ERROR == enet_software_reset()) {
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while (1);
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}
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#if (1 == _ENET_HARDWARE_CHECKSUM)
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if (ERROR == enet_init(ENET_AUTO_NEGOTIATION, ENET_AUTOCHECKSUM_DROP_FAILFRAMES, ENET_BROADCAST_FRAMES_PASS)) {
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while (1);
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}
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#else
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if (ERROR == enet_init(ENET_AUTO_NEGOTIATION, ENET_NO_AUTOCHECKSUM, ENET_BROADCAST_FRAMES_PASS)) {
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while (1);
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}
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#endif
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/* initialize MAC address in ethernet MAC */
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enet_mac_address_set(ENET_MAC_ADDRESS0, macaddr);
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enet_interrupt_enable(ENET_DMA_INT_NIE);
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enet_interrupt_enable(ENET_DMA_INT_RIE);
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/* Initialize Tx Descriptors list: Chain Mode */
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enet_descriptors_chain_init(ENET_DMA_TX);
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#if (1 == _ENET_HARDWARE_CHECKSUM)
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/* enable the TCP, UDP and ICMP checksum insertion for the Tx frames */
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for (i = 0; i < ENET_TXBUF_NUM; i++) {
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enet_transmit_checksum_config(&txdesc_tab[i], ENET_CHECKSUM_TCPUDPICMP_FULL);
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}
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#endif
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/* Initialize Rx Descriptors list: Chain Mode */
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enet_descriptors_chain_init(ENET_DMA_RX);
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/* enable ethernet Rx interrrupt */
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for (i = 0; i < ENET_RXBUF_NUM; i++) {
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enet_rx_desc_immediate_receive_complete_interrupt(&rxdesc_tab[i]);
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}
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/* enable MAC and DMA transmission and reception */
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enet_enable();
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return true;
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}
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/**
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* Sends the packet over the link
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*
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* That can not be called from an interrupt context.
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*
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* @param buf Packet to be send
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* @return True if the packet was send successfully, False otherwise
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*/
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bool GD32_EMAC::link_out(emac_mem_buf_t *buf)
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{
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emac_mem_buf_t *q;
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uint8_t *buffer;
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uint16_t framelength = 0;
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/* Get exclusive access */
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TXLockMutex.lock();
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while ((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)) {}
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/* copy frame from pbufs to driver buffers */
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buffer = reinterpret_cast<uint8_t *>(enet_desc_information_get(dma_current_txdesc, TXDESC_BUFFER_1_ADDR));
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for (q = buf; q != NULL; q = memory_manager->get_next(q)) {
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memcpy(static_cast<uint8_t *>(&buffer[framelength]), static_cast<uint8_t *>(memory_manager->get_ptr(q)), memory_manager->get_len(q));
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framelength = framelength + memory_manager->get_len(q);
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}
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/* Prepare transmit descriptors to give to DMA */
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if (SUCCESS != ENET_NOCOPY_FRAME_TRANSMIT(framelength)) {
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while (1);
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}
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memory_manager->free(buf);
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/* Restore access */
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TXLockMutex.unlock();
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return true;
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}
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/** \brief Attempt to read a packet from the EMAC interface.
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*
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*/
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emac_mem_buf_t *GD32_EMAC::low_level_input(void)
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{
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emac_mem_buf_t *p = NULL, *q;
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uint32_t l = 0;
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uint16_t len;
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uint8_t *buffer;
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/* obtain the size of the packet and put it into the "len" variable. */
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len = enet_desc_information_get(dma_current_rxdesc, RXDESC_FRAME_LENGTH);
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buffer = reinterpret_cast<uint8_t *>(enet_desc_information_get(dma_current_rxdesc, RXDESC_BUFFER_1_ADDR));
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if (len > 0) {
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/* Allocate a memory buffer chain from buffer pool */
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p = memory_manager->alloc_pool(len, 0);
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} else {
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return p;
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}
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if (p != NULL) {
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for (q = p; q != NULL; q = memory_manager->get_next(q)) {
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memcpy(static_cast<uint8_t *>(memory_manager->get_ptr(q)), static_cast<uint8_t *>(&buffer[l]), memory_manager->get_len(q));
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l = l + memory_manager->get_len(q);
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}
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}
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ENET_NOCOPY_FRAME_RECEIVE();
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return p;
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}
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/** \brief Attempt to read a packet from the EMAC interface.
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*
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*/
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void GD32_EMAC::packet_rx()
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{
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/* move received packet into a new buf */
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while (1) {
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emac_mem_buf_t *p = NULL;
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p = low_level_input();
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if (p) {
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emac_link_input_cb(p);
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} else {
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break;
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}
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}
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}
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/** \brief Worker thread.
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*
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* Woken by thread flags to receive packets or clean up transmit
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*
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* \param[in] pvParameters pointer to the interface data
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*/
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void GD32_EMAC::thread_function(void *pvParameters)
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{
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static struct GD32_EMAC *gd32_enet = static_cast<GD32_EMAC *>(pvParameters);
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while (1) {
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uint32_t flags = osThreadFlagsWait(_ENET_FLAG_RX, osFlagsWaitAny, osWaitForever);
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if (flags & _ENET_FLAG_RX) {
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gd32_enet->packet_rx();
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}
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}
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}
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/**
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* This task checks phy link status and updates net status
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*/
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void GD32_EMAC::phy_task()
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{
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uint16_t regval;
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enet_phy_write_read(ENET_PHY_READ, _ENET_BOARD_PHY_ADDRESS, PHY_REG_BSR, ®val);
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if (emac_link_state_cb) {
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regval &= PHY_LINKED_STATUS;
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if (phy_status != regval) {
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if (regval == PHY_LINKED_STATUS) {
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emac_link_state_cb(true);;
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} else {
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emac_link_state_cb(false);
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}
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}
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}
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phy_status = regval;
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}
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void GD32_EMAC::eth_arch_enable_interrupts(void)
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{
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nvic_irq_enable(ENET_IRQn, 7, 0);
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}
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void GD32_EMAC::eth_arch_disable_interrupts(void)
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{
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nvic_irq_disable(ENET_IRQn);
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}
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/** This returns a unique 6-byte MAC address, based on the device UID
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* This function overrides hal/common/mbed_interface.c function
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* @param mac A 6-byte array to write the MAC address
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*/
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void mbed_mac_address(char *mac)
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{
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uint32_t unique_id;
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unique_id = *(uint32_t *)_GD32_ID_ADDR;
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mac[0] = _GD_MAC_ADDR0;
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mac[1] = _GD_MAC_ADDR1;
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mac[2] = _GD_MAC_ADDR2;
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mac[3] = (unique_id & 0x00ff0000) >> 16;
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mac[4] = (unique_id & 0x0000ff00) >> 8;
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mac[5] = (unique_id & 0x000000ff);
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}
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/**
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* Initializes the HW
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*
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* @return True on success, False in case of an error.
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*/
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bool GD32_EMAC::power_up()
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{
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/* Initialize the hardware */
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if (true != low_level_init()) {
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return false;
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}
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/* Worker thread */
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rx_thread = create_new_thread("gd32_emac_thread", &GD32_EMAC::thread_function, this, _THREAD_STACKSIZE, _THREAD_PRIORITY, &rx_thread_cb);
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phy_task_handle = mbed::mbed_event_queue()->call_every(_PHY_TASK_PERIOD_MS, mbed::callback(this, &GD32_EMAC::phy_task));
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/* Allow the PHY task to detect the initial link state and set up the proper flags */
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osDelay(10);
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eth_arch_enable_interrupts();
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return true;
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}
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/**
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* Return maximum transmission unit
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*
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* @return MTU in bytes
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*/
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uint32_t GD32_EMAC::get_mtu_size() const
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{
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return _ENET_MTU_SIZE;
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}
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/**
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* Gets memory buffer alignment preference
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*
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* Gets preferred memory buffer alignment of the Emac device. IP stack may or may not
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* align link out memory buffer chains using the alignment.
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*
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* @return Memory alignment requirement in bytes
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*/
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uint32_t GD32_EMAC::get_align_preference() const
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{
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return 0;
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}
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/**
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* Return interface name
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*
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* @param name Pointer to where the name should be written
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* @param size Maximum number of character to copy
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*/
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void GD32_EMAC::get_ifname(char *name, uint8_t size) const
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{
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memcpy(name, _ENET_IF_NAME, (size < sizeof(_ENET_IF_NAME)) ? size : sizeof(_ENET_IF_NAME));
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}
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/**
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* Returns size of the underlying interface HW address size.
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*
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* @return HW address size in bytes
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*/
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uint8_t GD32_EMAC::get_hwaddr_size() const
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{
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return _ENET_HW_ADDR_SIZE;
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}
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/**
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* Returns size of the underlying interface HW address size.
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*
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* @return HW address size in bytes
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*/
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bool GD32_EMAC::get_hwaddr(uint8_t *addr) const
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{
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mbed_mac_address((char *)addr);
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return true;
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}
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/**
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* Set HW address for interface
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*
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* Provided address has to be of correct size, see @a get_hwaddr_size
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*
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* Called to set the MAC address to actually use - if @a get_hwaddr is provided
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* the stack would normally use that, but it could be overridden, eg for test
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* purposes.
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*
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* @param addr Address to be set
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*/
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void GD32_EMAC::set_hwaddr(const uint8_t *addr)
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{
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/* No-op at this stage */
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}
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/**
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* Sets a callback that needs to be called for packets received for that interface
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*
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* @param input_cb Function to be register as a callback
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*/
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void GD32_EMAC::set_link_input_cb(emac_link_input_cb_t input_cb)
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{
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emac_link_input_cb = input_cb;
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}
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/**
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* Sets a callback that needs to be called on link status changes for given interface
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*
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* @param state_cb Function to be register as a callback
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*/
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void GD32_EMAC::set_link_state_cb(emac_link_state_change_cb_t state_cb)
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{
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emac_link_state_cb = state_cb;
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}
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/** Add device to a multicast group
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*
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* @param address A multicast group hardware address
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*/
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void GD32_EMAC::add_multicast_group(const uint8_t *addr)
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{
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/* No-op at this stage */
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}
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/** Remove device from a multicast group
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*
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* @param address A multicast group hardware address
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*/
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void GD32_EMAC::remove_multicast_group(const uint8_t *addr)
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{
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/* No-op at this stage */
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}
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/** Request reception of all multicast packets
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*
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* @param all True to receive all multicasts
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* False to receive only multicasts addressed to specified groups
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*/
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void GD32_EMAC::set_all_multicast(bool all)
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{
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/* No-op at this stage */
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}
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/**
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* Deinitializes the HW
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*
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*/
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void GD32_EMAC::power_down()
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{
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/* No-op at this stage */
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}
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/** Sets memory manager that is used to handle memory buffers
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*
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* @param mem_mngr Pointer to memory manager
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*/
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void GD32_EMAC::set_memory_manager(EMACMemoryManager &mem_mngr)
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{
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memory_manager = &mem_mngr;
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}
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GD32_EMAC &GD32_EMAC::get_instance()
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{
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static GD32_EMAC emac;
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return emac;
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}
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|
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/* Weak so a module can override */
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MBED_WEAK EMAC &EMAC::get_default_instance()
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{
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return GD32_EMAC::get_instance();
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}
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>>>>>>> 644cc537cff06b20c3155fe0dea2ac62d567c3c3
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