mirror of https://github.com/ARMmbed/mbed-os.git
381 lines
35 KiB
C
381 lines
35 KiB
C
/**
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* @file
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* @brief Type definitions for the Watchdog Timer Peripheral
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*
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*/
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/* ****************************************************************************
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* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
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* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Except as contained in this notice, the name of Maxim Integrated
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* Products, Inc. shall not be used except as stated in the Maxim Integrated
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* Products, Inc. Branding Policy.
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*
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* The mere transfer of this software does not imply any licenses
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* of trade secrets, proprietary technology, copyrights, patents,
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* trademarks, maskwork rights, or any other form of intellectual
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* property whatsoever. Maxim Integrated Products, Inc. retains all
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* ownership rights.
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*
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* $Date: 2016-10-10 19:53:06 -0500 (Mon, 10 Oct 2016) $
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* $Revision: 24677 $
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*
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*
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**************************************************************************** */
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/* Define to prevent redundant inclusion */
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#ifndef _MXC_WDT_REGS_H_
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#define _MXC_WDT_REGS_H_
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/* **** Includes **** */
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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///@cond
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/*
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If types are not defined elsewhere (CMSIS) define them here
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*/
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#ifndef __IO
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#define __IO volatile
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#endif
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#ifndef __I
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#define __I volatile const
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#endif
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#ifndef __O
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#define __O volatile
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#endif
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#ifndef __RO
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#define __RO volatile const
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#endif
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///@endcond
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/**
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* @ingroup wdt0
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* @defgroup wdt_registers Registers
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* @brief Registers, Bit Masks and Bit Positions
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* @{
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*/
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/*
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Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
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access to each register in module.
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*/
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/**
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* Structure type to access the WDT Registers, see #MXC_WDT_GET_WDT(i) to get a pointer to the WDT[i] register structure.
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* @note For the Always-On Watch Dog Timer, see \ref wdt2.
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*/
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typedef struct {
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__IO uint32_t ctrl; /**< <tt>\b 0x0000:</tt> WDT_CTRL Register - WDT Control Register */
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__IO uint32_t clear; /**< <tt>\b 0x0004:</tt> WDT_CLEAR Register - WDT Clear Register to prevent a WDT Reset (Feed Dog) */
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__IO uint32_t flags; /**< <tt>\b 0x0008:</tt> WDT_FLAGS Register - WDT Interrupt and Reset Flags */
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__IO uint32_t enable; /**< <tt>\b 0x000C:</tt> WDT_ENABLE Register - WDT Reset and Interrupt Enable/Disable Controls */
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__RO uint32_t rsv010; /**< <tt>\b 0x0010:</tt> RESERVED, DO NOT MODIFY. */
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__IO uint32_t lock_ctrl; /**< <tt>\b 0x0014:</tt> WDT_LOCK_CTRL Register - Lock for Control Register */
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} mxc_wdt_regs_t;
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/**@} end of group wdt_registers.*/
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/*
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Register offsets for module WDT.
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*/
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/**
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* @ingroup wdt_registers
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* @defgroup WDT_Register_Offsets Register Offsets
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* @brief Watchdog Timer Register Offsets from the WDT[n] Base Peripheral Address, where n is between 0 and #MXC_CFG_WDT_INSTANCES for the \MXIM_Device.
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* @details Use #MXC_WDT_GET_BASE(i) to get the base address for a specific watchdog timer instance.
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* @note See \ref wdt2 for the Always-On Watchdog Timer Peripheral driver.
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* @{
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*/
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#define MXC_R_WDT_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from the WDT[i] Base Peripheral Address : WDT_CTRL : <tt>\b 0x0000 </tt> */
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#define MXC_R_WDT_OFFS_CLEAR ((uint32_t)0x00000004UL) /**< Offset from the WDT[i] Base Peripheral Address : WDT_CLEAR : <tt>\b 0x0004 </tt> */
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#define MXC_R_WDT_OFFS_FLAGS ((uint32_t)0x00000008UL) /**< Offset from the WDT[i] Base Peripheral Address : WDT_FLAGS : <tt>\b 0x0008 </tt> */
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#define MXC_R_WDT_OFFS_ENABLE ((uint32_t)0x0000000CUL) /**< Offset from the WDT[i] Base Peripheral Address : WDT_ENABLE : <tt>\b 0x000C </tt> */
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#define MXC_R_WDT_OFFS_LOCK_CTRL ((uint32_t)0x00000014UL) /**< Offset from the WDT[i] Base Peripheral Address : WDT_LOCK_CTRL : <tt>\b 0x0014 </tt> */
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/**@} end of group WDT_Register_Offsets */
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/*
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Field positions and masks for module WDT.
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*/
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/**
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* @ingroup wdt_registers
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* @defgroup WDT_CTRL_Register WDT_CTRL Register
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* @brief Field Positions and Bit Masks for the WDT_CTRL register
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* @{
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*/
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#define MXC_F_WDT_CTRL_INT_PERIOD_POS 0 /**< INT_PERIOD Field Position */
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#define MXC_F_WDT_CTRL_INT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< INT_PERIOD Field Mask - This field is used to set the interrupt period on the WDT. */
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#define MXC_F_WDT_CTRL_RST_PERIOD_POS 4 /**< RST_PERIOD Field Position */
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#define MXC_F_WDT_CTRL_RST_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< RST_PERIOD Field Mask - This field sets the time after an
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* interrupt period has expired before the device resets. If the
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* INT_PERIOD Flag is cleared prior to the RST_PERIOD expiration,
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* the device will not reset. */
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#define MXC_F_WDT_CTRL_EN_TIMER_POS 8 /**< EN_TIMER Field Position */
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#define MXC_F_WDT_CTRL_EN_TIMER ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_TIMER_POS)) /**< EN_TIMER Field Mask */
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#define MXC_F_WDT_CTRL_EN_CLOCK_POS 9 /**< EN_CLOCK Field Position */
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#define MXC_F_WDT_CTRL_EN_CLOCK ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_CLOCK_POS)) /**< EN_CLOCK Field Mask */
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#define MXC_F_WDT_CTRL_WAIT_PERIOD_POS 12 /**< WAIT_PERIOD Field Position */
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#define MXC_F_WDT_CTRL_WAIT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< WAIT_PERIOD Field Mask */
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/**@} end of group WDT_CTRL */
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/**
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* @ingroup wdt_registers
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* @defgroup WDT_FLAGS_Register WDT_FLAGS Register
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* @brief Field Positions and Bit Masks for the WDT_FLAGS register. Watchdog Timer Flags for Interrupts and Reset.
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* @{
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*/
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#define MXC_F_WDT_FLAGS_TIMEOUT_POS 0 /**< TIMEOUT Flag Position */
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#define MXC_F_WDT_FLAGS_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_TIMEOUT_POS)) /**< TIMEOUT Flag Mask - if this flag is set it indicates the Watchdog Timer timed out. */
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#define MXC_F_WDT_FLAGS_PRE_WIN_POS 1 /**< PRE_WIN Flag Position */
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#define MXC_F_WDT_FLAGS_PRE_WIN ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_PRE_WIN_POS)) /**< PRE_WIN Flag Mask - If the PRE_WIN flag is set it indicates the Watchdog Timer was cleared by firmware writing to the WDT_CLEAR register <b><em> during the pre-window period</em></b>. */
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#define MXC_F_WDT_FLAGS_RESET_OUT_POS 2 /**< RESET_OUT Flag Position */
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#define MXC_F_WDT_FLAGS_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_RESET_OUT_POS)) /**< RESET_FLAG Flag Mask - This flag indicates that the watchdog timer timed out and the reset period elapsed without the timer being cleared. This will result in a system restart. */
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/**@} end of group WDT_FLAGS */
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/**
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* @ingroup wdt_registers
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* @defgroup WDT_ENABLE_Register WDT_ENABLE Register
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* @brief Field Positions and Bit Masks for the WDT_ENABLE register.
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* @{
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*/
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#define MXC_F_WDT_ENABLE_TIMEOUT_POS 0 /**< ENABLE_TIMEOUT Field Position */
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#define MXC_F_WDT_ENABLE_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_TIMEOUT_POS)) /**< ENABLE_TIMEOUT Field Mask */
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#define MXC_F_WDT_ENABLE_PRE_WIN_POS 1 /**< ENABLE_PRE_WIN Field Position */
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#define MXC_F_WDT_ENABLE_PRE_WIN ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_PRE_WIN_POS)) /**< ENABLE_PRE_WIN Field Mask */
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#define MXC_F_WDT_ENABLE_RESET_OUT_POS 2 /**< ENABLE_RESET_OUT Field Position */
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#define MXC_F_WDT_ENABLE_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_RESET_OUT_POS)) /**< ENABLE_RESET_OUT Field Mask */
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/**@} end of group WDT_ENABLE */
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/**
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* @ingroup wdt_registers
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* @defgroup WDT_LOCK_CTRL_Register WDT_LOCK_CTRL Register
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* @brief The WDT_LOCK_CTRL register controls read/write access to the \ref WDT_CTRL_Register.
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* @{
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*/
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#define MXC_F_WDT_LOCK_CTRL_WDLOCK_POS 0 /**< WDLOCK Field's position in the WDT_LOCK_CTRL register. */
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#define MXC_F_WDT_LOCK_CTRL_WDLOCK ((uint32_t)(0x000000FFUL << MXC_F_WDT_LOCK_CTRL_WDLOCK_POS)) /**< WDLOCK Field mask for the WDT_LOCK_CTRL register. Reading a value of */
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/**@} end of group WDT_ENABLE */
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/*
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Field values and shifted values for module WDT.
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*/
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/**
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* @ingroup WDT_CTRL_Register
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* @defgroup WDT_CTRL_field_values WDT_CTRL Register Field and Shifted Field Values
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* @brief Field values and Shifted Field values for the WDT_CTRL register.
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* @details Shifted field values are field values shifted to the loacation of the field in the register.
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*/
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/**
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* @ingroup WDT_CTRL_field_values
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* @defgroup WDT_CTRL_INT_PERIOD_Value Watchdog Timer Interrupt Period
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* @brief Sets the duration of the watchdog interrupt period.
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* @details The INT_PERIOD field sets the duration of the watchdog interrupt
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* period, which is the time period from the WDT being
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* enabled/cleared until the WDT flag, #MXC_F_WDT_FLAGS_TIMEOUT, is
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* set.
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* The values defined are in the number of watchdog clock cycles.
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* @{
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*/
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#define MXC_V_WDT_CTRL_INT_PERIOD_2_31_CLKS ((uint32_t)(0x00000000UL)) /**< Interupt Period of \f$ 2^{31} \f$ WDT CLK Cycles */
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#define MXC_V_WDT_CTRL_INT_PERIOD_2_30_CLKS ((uint32_t)(0x00000001UL)) /**< Interupt Period of \f$ 2^{30} \f$ WDT CLK Cycles */
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#define MXC_V_WDT_CTRL_INT_PERIOD_2_29_CLKS ((uint32_t)(0x00000002UL)) /**< Interupt Period of \f$ 2^{29} \f$ WDT CLK Cycles */
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#define MXC_V_WDT_CTRL_INT_PERIOD_2_28_CLKS ((uint32_t)(0x00000003UL)) /**< Interupt Period of \f$ 2^{28} \f$ WDT CLK Cycles */
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#define MXC_V_WDT_CTRL_INT_PERIOD_2_27_CLKS ((uint32_t)(0x00000004UL)) /**< Interupt Period of \f$ 2^{27} \f$ WDT CLK Cycles */
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#define MXC_V_WDT_CTRL_INT_PERIOD_2_26_CLKS ((uint32_t)(0x00000005UL)) /**< Interupt Period of \f$ 2^{26} \f$ WDT CLK Cycles */
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#define MXC_V_WDT_CTRL_INT_PERIOD_2_25_CLKS ((uint32_t)(0x00000006UL)) /**< Interupt Period of \f$ 2^{25} \f$ WDT CLK Cycles */
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#define MXC_V_WDT_CTRL_INT_PERIOD_2_24_CLKS ((uint32_t)(0x00000007UL)) /**< Interupt Period of \f$ 2^{24} \f$ WDT CLK Cycles */
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#define MXC_V_WDT_CTRL_INT_PERIOD_2_23_CLKS ((uint32_t)(0x00000008UL)) /**< Interupt Period of \f$ 2^{23} \f$ WDT CLK Cycles */
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#define MXC_V_WDT_CTRL_INT_PERIOD_2_22_CLKS ((uint32_t)(0x00000009UL)) /**< Interupt Period of \f$ 2^{22} \f$ WDT CLK Cycles */
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#define MXC_V_WDT_CTRL_INT_PERIOD_2_21_CLKS ((uint32_t)(0x0000000AUL)) /**< Interupt Period of \f$ 2^{21} \f$ WDT CLK Cycles */
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#define MXC_V_WDT_CTRL_INT_PERIOD_2_20_CLKS ((uint32_t)(0x0000000BUL)) /**< Interupt Period of \f$ 2^{20} \f$ WDT CLK Cycles */
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#define MXC_V_WDT_CTRL_INT_PERIOD_2_19_CLKS ((uint32_t)(0x0000000CUL)) /**< Interupt Period of \f$ 2^{19} \f$ WDT CLK Cycles */
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#define MXC_V_WDT_CTRL_INT_PERIOD_2_18_CLKS ((uint32_t)(0x0000000DUL)) /**< Interupt Period of \f$ 2^{18} \f$ WDT CLK Cycles */
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#define MXC_V_WDT_CTRL_INT_PERIOD_2_17_CLKS ((uint32_t)(0x0000000EUL)) /**< Interupt Period of \f$ 2^{17} \f$ WDT CLK Cycles */
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#define MXC_V_WDT_CTRL_INT_PERIOD_2_16_CLKS ((uint32_t)(0x0000000FUL)) /**< Interupt Period of \f$ 2^{16} \f$ WDT CLK Cycles */
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/**@} end of group WDT_CTRL_INT_PERIOD_Value */
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/**
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* @ingroup WDT_CTRL_field_values
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* @defgroup WDT_CTRL_INT_PERIOD_Shifted Watchdog Timer Interrupt Period Shifted Values
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* @brief Shifted values for the \ref WDT_CTRL_INT_PERIOD_Value
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* @details The shifted value is
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* shifted to align with the fields location in the WDT_CTRL register.
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* @{
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*/
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#define MXC_S_WDT_CTRL_INT_PERIOD_2_31_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_31_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_31_CLKS */
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#define MXC_S_WDT_CTRL_INT_PERIOD_2_30_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_30_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_30_CLKS */
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#define MXC_S_WDT_CTRL_INT_PERIOD_2_29_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_29_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_29_CLKS */
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#define MXC_S_WDT_CTRL_INT_PERIOD_2_28_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_28_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_28_CLKS */
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#define MXC_S_WDT_CTRL_INT_PERIOD_2_27_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_27_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_27_CLKS */
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#define MXC_S_WDT_CTRL_INT_PERIOD_2_26_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_26_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_26_CLKS */
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#define MXC_S_WDT_CTRL_INT_PERIOD_2_25_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_25_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_25_CLKS */
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#define MXC_S_WDT_CTRL_INT_PERIOD_2_24_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_24_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_24_CLKS */
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#define MXC_S_WDT_CTRL_INT_PERIOD_2_23_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_23_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_23_CLKS */
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#define MXC_S_WDT_CTRL_INT_PERIOD_2_22_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_22_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_22_CLKS */
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#define MXC_S_WDT_CTRL_INT_PERIOD_2_21_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_21_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_21_CLKS */
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#define MXC_S_WDT_CTRL_INT_PERIOD_2_20_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_20_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_20_CLKS */
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#define MXC_S_WDT_CTRL_INT_PERIOD_2_19_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_19_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_19_CLKS */
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#define MXC_S_WDT_CTRL_INT_PERIOD_2_18_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_18_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_18_CLKS */
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#define MXC_S_WDT_CTRL_INT_PERIOD_2_17_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_17_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_17_CLKS */
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#define MXC_S_WDT_CTRL_INT_PERIOD_2_16_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_16_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_16_CLKS */
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/**@} end of group WDT_CTRL_INT_PERIOD_Shifted */
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/**
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* @ingroup WDT_CTRL_field_values
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* @defgroup WDT_CTRL_RST_PERIOD_Value Watchdog Timer Reset Period
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* @brief Sets the duration of the watchdog reset period.
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* @details The RST_PERIOD field sets the duration of the watchdog reset
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* period, which is the time period from the WDT being
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* enabled/cleared until the WDT flag, #MXC_F_WDT_CTRL_RST_PERIOD is
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* set.
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* The values defined are in the number of watchdog clock cycles.
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* @{
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*/
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#define MXC_V_WDT_CTRL_RST_PERIOD_2_31_CLKS ((uint32_t)(0x00000000UL)) /**< Reset Period of \f$ 2^{31} \f$ WDT CLK CYCLES */
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#define MXC_V_WDT_CTRL_RST_PERIOD_2_30_CLKS ((uint32_t)(0x00000001UL)) /**< Reset Period of \f$ 2^{30} \f$ WDT CLK CYCLES */
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#define MXC_V_WDT_CTRL_RST_PERIOD_2_29_CLKS ((uint32_t)(0x00000002UL)) /**< Reset Period of \f$ 2^{29} \f$ WDT CLK CYCLES */
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#define MXC_V_WDT_CTRL_RST_PERIOD_2_28_CLKS ((uint32_t)(0x00000003UL)) /**< Reset Period of \f$ 2^{28} \f$ WDT CLK CYCLES */
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#define MXC_V_WDT_CTRL_RST_PERIOD_2_27_CLKS ((uint32_t)(0x00000004UL)) /**< Reset Period of \f$ 2^{27} \f$ WDT CLK CYCLES */
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#define MXC_V_WDT_CTRL_RST_PERIOD_2_26_CLKS ((uint32_t)(0x00000005UL)) /**< Reset Period of \f$ 2^{26} \f$ WDT CLK CYCLES */
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#define MXC_V_WDT_CTRL_RST_PERIOD_2_25_CLKS ((uint32_t)(0x00000006UL)) /**< Reset Period of \f$ 2^{25} \f$ WDT CLK CYCLES */
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#define MXC_V_WDT_CTRL_RST_PERIOD_2_24_CLKS ((uint32_t)(0x00000007UL)) /**< Reset Period of \f$ 2^{24} \f$ WDT CLK CYCLES */
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#define MXC_V_WDT_CTRL_RST_PERIOD_2_23_CLKS ((uint32_t)(0x00000008UL)) /**< Reset Period of \f$ 2^{23} \f$ WDT CLK CYCLES */
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#define MXC_V_WDT_CTRL_RST_PERIOD_2_22_CLKS ((uint32_t)(0x00000009UL)) /**< Reset Period of \f$ 2^{22} \f$ WDT CLK CYCLES */
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#define MXC_V_WDT_CTRL_RST_PERIOD_2_21_CLKS ((uint32_t)(0x0000000AUL)) /**< Reset Period of \f$ 2^{21} \f$ WDT CLK CYCLES */
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#define MXC_V_WDT_CTRL_RST_PERIOD_2_20_CLKS ((uint32_t)(0x0000000BUL)) /**< Reset Period of \f$ 2^{20} \f$ WDT CLK CYCLES */
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#define MXC_V_WDT_CTRL_RST_PERIOD_2_19_CLKS ((uint32_t)(0x0000000CUL)) /**< Reset Period of \f$ 2^{19} \f$ WDT CLK CYCLES */
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#define MXC_V_WDT_CTRL_RST_PERIOD_2_18_CLKS ((uint32_t)(0x0000000DUL)) /**< Reset Period of \f$ 2^{18} \f$ WDT CLK CYCLES */
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#define MXC_V_WDT_CTRL_RST_PERIOD_2_17_CLKS ((uint32_t)(0x0000000EUL)) /**< Reset Period of \f$ 2^{17} \f$ WDT CLK CYCLES */
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#define MXC_V_WDT_CTRL_RST_PERIOD_2_16_CLKS ((uint32_t)(0x0000000FUL)) /**< Reset Period of \f$ 2^{16} \f$ WDT CLK CYCLES */
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/**@} end of group WDT_CTRL_RST_PERIOD_Value */
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/**
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* @ingroup WDT_CTRL_field_values
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* @defgroup WDT_CTRL_RST_PERIOD_Shifted Watchdog Timer Reset Period Shifted Values
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* @brief Shifted values for the \ref WDT_CTRL_RST_PERIOD_Value
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* @details These values are shifted to align with the field's location in the WDT_CTRL register.
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* @{
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*/
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#define MXC_S_WDT_CTRL_RST_PERIOD_2_31_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_31_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_31_CLKS */
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#define MXC_S_WDT_CTRL_RST_PERIOD_2_30_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_30_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_30_CLKS */
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#define MXC_S_WDT_CTRL_RST_PERIOD_2_29_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_29_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_29_CLKS */
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#define MXC_S_WDT_CTRL_RST_PERIOD_2_28_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_28_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_28_CLKS */
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#define MXC_S_WDT_CTRL_RST_PERIOD_2_27_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_27_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_27_CLKS */
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#define MXC_S_WDT_CTRL_RST_PERIOD_2_26_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_26_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_26_CLKS */
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#define MXC_S_WDT_CTRL_RST_PERIOD_2_25_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_25_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_25_CLKS */
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#define MXC_S_WDT_CTRL_RST_PERIOD_2_24_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_24_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_24_CLKS */
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#define MXC_S_WDT_CTRL_RST_PERIOD_2_23_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_23_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_23_CLKS */
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#define MXC_S_WDT_CTRL_RST_PERIOD_2_22_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_22_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_22_CLKS */
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#define MXC_S_WDT_CTRL_RST_PERIOD_2_21_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_21_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_21_CLKS */
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#define MXC_S_WDT_CTRL_RST_PERIOD_2_20_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_20_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_20_CLKS */
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#define MXC_S_WDT_CTRL_RST_PERIOD_2_19_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_19_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_19_CLKS */
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#define MXC_S_WDT_CTRL_RST_PERIOD_2_18_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_18_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_18_CLKS */
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#define MXC_S_WDT_CTRL_RST_PERIOD_2_17_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_17_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_17_CLKS */
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#define MXC_S_WDT_CTRL_RST_PERIOD_2_16_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_16_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_16_CLKS */
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/**@} end of group WDT_CTRL_RST_PERIOD_Shifted */
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/**
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* @ingroup WDT_CTRL_field_values
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* @defgroup WDT_CTRL_WAIT_PERIOD_Value Watchdog Timer Wait Period
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* @brief Sets the duration of the watchdog wait window period.
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* @details The WAIT_PERIOD field sets the duration of the watchdog pre-window
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* period. If the watchdog is reset before the wait period has finished, an out-of-window interrupt will occur.
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* This sets the minimum amount of time between watchdog enable/clear to resetting the WDT count and assists in detecting
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* overclocking or an invalid clock.
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* The values defined are in the number of watchdog clock cycles.
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* @{
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*/
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#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_31_CLKS ((uint32_t)(0x00000000UL)) /**< Wait Period of \f$ 2^{31} \f$ WDT CLK CYCLES */
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#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_30_CLKS ((uint32_t)(0x00000001UL)) /**< Wait Period of \f$ 2^{30} \f$ WDT CLK CYCLES */
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#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_29_CLKS ((uint32_t)(0x00000002UL)) /**< Wait Period of \f$ 2^{29} \f$ WDT CLK CYCLES */
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#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_28_CLKS ((uint32_t)(0x00000003UL)) /**< Wait Period of \f$ 2^{28} \f$ WDT CLK CYCLES */
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#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_27_CLKS ((uint32_t)(0x00000004UL)) /**< Wait Period of \f$ 2^{27} \f$ WDT CLK CYCLES */
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#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_26_CLKS ((uint32_t)(0x00000005UL)) /**< Wait Period of \f$ 2^{26} \f$ WDT CLK CYCLES */
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#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_25_CLKS ((uint32_t)(0x00000006UL)) /**< Wait Period of \f$ 2^{25} \f$ WDT CLK CYCLES */
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#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_24_CLKS ((uint32_t)(0x00000007UL)) /**< Wait Period of \f$ 2^{24} \f$ WDT CLK CYCLES */
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#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_23_CLKS ((uint32_t)(0x00000008UL)) /**< Wait Period of \f$ 2^{23} \f$ WDT CLK CYCLES */
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#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_22_CLKS ((uint32_t)(0x00000009UL)) /**< Wait Period of \f$ 2^{22} \f$ WDT CLK CYCLES */
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#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_21_CLKS ((uint32_t)(0x0000000AUL)) /**< Wait Period of \f$ 2^{21} \f$ WDT CLK CYCLES */
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#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_20_CLKS ((uint32_t)(0x0000000BUL)) /**< Wait Period of \f$ 2^{20} \f$ WDT CLK CYCLES */
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#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_19_CLKS ((uint32_t)(0x0000000CUL)) /**< Wait Period of \f$ 2^{19} \f$ WDT CLK CYCLES */
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#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_18_CLKS ((uint32_t)(0x0000000DUL)) /**< Wait Period of \f$ 2^{18} \f$ WDT CLK CYCLES */
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#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_17_CLKS ((uint32_t)(0x0000000EUL)) /**< Wait Period of \f$ 2^{17} \f$ WDT CLK CYCLES */
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#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_16_CLKS ((uint32_t)(0x0000000FUL)) /**< Wait Period of \f$ 2^{16} \f$ WDT CLK CYCLES */
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/**@} end of group WDT_CTRL_WAIT_PERIOD_Value */
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/**
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* @ingroup WDT_CTRL_field_values
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* @defgroup WDT_CTRL_WAIT_PERIOD_Shifted Watchdog Timer Wait Period Shifted Values
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* @brief Shifted values for the \ref WDT_CTRL_WAIT_PERIOD_Value
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* @details These values are shifted to align with the WAIT_PERIOD field's location in the WDT_CTRL register.
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* @{
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*/
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#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_31_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_31_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_31_CLKS */
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#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_30_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_30_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_30_CLKS */
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#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_29_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_29_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_29_CLKS */
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#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_28_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_28_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_28_CLKS */
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#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_27_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_27_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_27_CLKS */
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#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_26_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_26_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_26_CLKS */
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#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_25_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_25_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_25_CLKS */
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#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_24_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_24_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_24_CLKS */
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#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_23_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_23_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_23_CLKS */
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#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_22_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_22_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_22_CLKS */
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#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_21_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_21_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_21_CLKS */
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#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_20_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_20_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_20_CLKS */
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#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_19_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_19_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_19_CLKS */
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#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_18_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_18_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_18_CLKS */
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#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_17_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_17_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_17_CLKS */
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#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_16_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_16_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_16_CLKS */
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/**@} end of group WDT_CTRL_WAIT_PERIOD_Shifted */
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/**
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* @ingroup WDT_LOCK_CTRL_Register
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* @defgroup WDT_LOCK_field_values Watchdog Timer WDT_LOCK field values
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* @brief Lock/Unlock values for the watchdog timer \ref WDT_CTRL_Register.
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* @{
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*/
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#define MXC_V_WDT_LOCK_KEY 0x24 /**< Writing this value to the WDT_LOCK field of the \ref WDT_LOCK_CTRL_Register \b locks the \ref WDT_CTRL_Register making it read only. */
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#define MXC_V_WDT_UNLOCK_KEY 0x42 /**< Writing this value to the WDT_LOCK field of the \ref WDT_LOCK_CTRL_Register \b unlocks the \ref WDT_CTRL_Register making it read/write. */
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/**@} end of group WDT_LOCK_field_values */
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///@cond
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/*
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* @internal
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* @ingroup WDT_CLEAR_Register
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* @defgroup WDT_CLEAR_field_values Watchdog Timer Clear Sequence Values
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* @brief Writing the sequence of #MXC_V_WDT_RESET_KEY_0, #MXC_V_WDT_RESET_KEY_1 to the \ref WDT_CLEAR_Register will clear/reset the watchdog timer count.
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* @note The values #MXC_V_WDT_RESET_KEY_0, #MXC_V_WDT_RESET_KEY_1 must be written sequentially to the \ref WDT_CLEAR_Register to clear the watchdog counter.
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* @{
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*/
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#define MXC_V_WDT_RESET_KEY_0 0xA5 /**< First value to write to the \ref WDT_CLEAR_Register to perform a WDT clear. */
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#define MXC_V_WDT_RESET_KEY_1 0x5A /**< Second value to write to the \ref WDT_CLEAR_Register to perform a WDT clear. */
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/**
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* @} end of group WDT_CLEAR_field_values
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* @endinternal
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*/
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///@endcond
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/**@} wdt_registers*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* _MXC_WDT_REGS_H_ */
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