mirror of https://github.com/ARMmbed/mbed-os.git
158 lines
7.3 KiB
C
158 lines
7.3 KiB
C
/**
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* @file
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* @brief Registers, Bit Masks and Bit Positions for the Instruction Cache Controller.
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*/
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/* ****************************************************************************
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* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
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* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Except as contained in this notice, the name of Maxim Integrated
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* Products, Inc. shall not be used except as stated in the Maxim Integrated
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* Products, Inc. Branding Policy.
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*
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* The mere transfer of this software does not imply any licenses
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* of trade secrets, proprietary technology, copyrights, patents,
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* trademarks, maskwork rights, or any other form of intellectual
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* property whatsoever. Maxim Integrated Products, Inc. retains all
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* ownership rights.
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*
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* $Date: 2016-10-10 19:01:16 -0500 (Mon, 10 Oct 2016) $
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* $Revision: 24662 $
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*
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*************************************************************************** */
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/* Define to prevent redundant inclusion */
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#ifndef _MXC_ICC_REGS_H_
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#define _MXC_ICC_REGS_H_
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/* **** Includes **** */
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/// @cond
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/*
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If types are not defined elsewhere (CMSIS) define them here
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*/
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#ifndef __IO
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#define __IO volatile
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#endif
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#ifndef __I
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#define __I volatile const
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#endif
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#ifndef __O
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#define __O volatile
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#endif
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#ifndef __RO
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#define __RO volatile const
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#endif
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///@endcond
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/* **** Definitions **** */
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/**
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* @ingroup icc
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* @defgroup icc_registers Registers
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* @brief Registers, Bit Masks and Bit Positions for the ICC.
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* @{
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*/
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/**
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* Structure type to access the ICC Registers.
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*/
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typedef struct {
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__IO uint32_t id; /**< <tt>\b 0x0000: </tt> ICC_ID Register \warning INTERNAL USE ONLY, DO NOT MODIFY */
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__IO uint32_t mem_cfg; /**< <tt>\b 0x0004: </tt> ICC_MEM_CFG Register */
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__RO uint32_t rsv008[62]; /**< <tt>\b 0x0008-0x00FC: </tt> RESERVED */
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__IO uint32_t ctrl_stat; /**< <tt>\b 0x0100: </tt> ICC_CTRL_STAT Register */
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__RO uint32_t rsv104[383]; /**< <tt>\b 0x0104-0x06FC: </tt> RESERVED */
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__IO uint32_t invdt_all; /**< <tt>\b 0x0700: </tt> ICC_INVDT_ALL Register */
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} mxc_icc_regs_t;
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/**@} end of group icc_registers*/
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/*
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Register offsets for module ICC.
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*/
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/**
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* @ingroup icc_registers
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* @defgroup ICC_Register_Offsets Register Offsets
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* @brief Instruction Cache Controller Register Offsets from the ICC Base Address.
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* @{
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*/
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#define MXC_R_ICC_OFFS_ID ((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: <tt>\b 0x0000</tt> */
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#define MXC_R_ICC_OFFS_MEM_CFG ((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: <tt>\b 0x0004</tt> */
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#define MXC_R_ICC_OFFS_CTRL_STAT ((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: <tt>\b 0x0100</tt> */
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#define MXC_R_ICC_OFFS_INVDT_ALL ((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: <tt>\b 0x0700</tt> */
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/**@} end of group icc_registers */
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/*
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Field positions and masks for module ICC.
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*/
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/**
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* @ingroup icc_registers
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* @defgroup ICC_ID_Register ICC_ID
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* @brief Field Positions and Bit Masks for the ICC_ID register
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* @{
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*/
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#define MXC_F_ICC_ID_RTL_VERSION_POS 0 /**< RTL_VERSION Position */
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#define MXC_F_ICC_ID_RTL_VERSION ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_RTL_VERSION_POS)) /**< RTL_VERSION Mask */
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#define MXC_F_ICC_ID_PART_NUM_POS 6 /**< PART_NUM Position */
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#define MXC_F_ICC_ID_PART_NUM ((uint32_t)(0x0000000FUL << MXC_F_ICC_ID_PART_NUM_POS)) /**< PART_NUM Mask */
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#define MXC_F_ICC_ID_CACHE_ID_POS 10 /**< CACHE_ID Position */
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#define MXC_F_ICC_ID_CACHE_ID ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_CACHE_ID_POS)) /**< CACHE_ID Mask */
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/**@} end of group ICC_ID_register */
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/**
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* @ingroup icc_registers
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* @defgroup ICC_MEM_CFG_Register ICC_MEM_CFG
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* @brief Field Positions and Bit Masks for the ICC_MEM_CFG register
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* @{
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*/
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#define MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS 0 /**< CACHE_SIZE Position */
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#define MXC_F_ICC_MEM_CFG_CACHE_SIZE ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS)) /**< CACHE_SIZE Mask */
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#define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS 16 /**< MAIN_MEMORY_SIZE Position */
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#define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS)) /**< MAIN_MEMORY_SIZE Mask */
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/**@} end of group ICC_MEM_CFG_register */
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/**
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* @ingroup icc_registers
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* @defgroup ICC_CTRL_STAT_Register ICC_CTRL_STAT
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* @brief Field Positions and Bit Masks for the ICC_CTRL_STAT register
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* @{
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*/
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#define MXC_F_ICC_CTRL_STAT_ENABLE_POS 0 /**< ENABLE Position */
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#define MXC_F_ICC_CTRL_STAT_ENABLE ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_ENABLE_POS)) /**< ENABLE Mask */
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#define MXC_F_ICC_CTRL_STAT_READY_POS 16 /**< READY Position */
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#define MXC_F_ICC_CTRL_STAT_READY ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_READY_POS)) /**< READY Mask */
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/**@} end of group ICC_CTRL_STAT_register */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _MXC_ICC_REGS_H_ */
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