mirror of https://github.com/ARMmbed/mbed-os.git
189 lines
14 KiB
C
189 lines
14 KiB
C
/**
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* @file
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* @brief Registers, Bit Masks and Bit Positions for the AES Peripheral Module.
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*/
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/* ****************************************************************************
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* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
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* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Except as contained in this notice, the name of Maxim Integrated
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* Products, Inc. shall not be used except as stated in the Maxim Integrated
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* Products, Inc. Branding Policy.
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*
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* The mere transfer of this software does not imply any licenses
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* of trade secrets, proprietary technology, copyrights, patents,
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* trademarks, maskwork rights, or any other form of intellectual
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* property whatsoever. Maxim Integrated Products, Inc. retains all
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* ownership rights.
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*
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* $Date: 2016-10-10 16:51:05 -0500 (Mon, 10 Oct 2016) $
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* $Revision: 24655 $
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*
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*************************************************************************** */
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/* Define to prevent redundant inclusion */
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#ifndef _MXC_AES_REGS_H_
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#define _MXC_AES_REGS_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* **** Includes **** */
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#include <stdint.h>
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/// @cond
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/*
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If types are not defined elsewhere (CMSIS) define them here
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*/
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#ifndef __IO
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#define __IO volatile
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#endif
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#ifndef __I
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#define __I volatile const
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#endif
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#ifndef __O
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#define __O volatile
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#endif
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#ifndef __RO
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#define __RO volatile const
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#endif
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/// @endcond
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/* **** Definitions **** */
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/**
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* @ingroup aes
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* @defgroup aes_registers Registers
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* @brief Registers, Bit Masks and Bit Positions for the AES Peripheral Module.
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* @{
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*/
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/**
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* Structure type to access the AES Registers.
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*/
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typedef struct {
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__IO uint32_t ctrl; /**< <tt>\b 0x0000:</tt> AES_CTRL Register */
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__RO uint32_t rsv004; /**< <tt>\b 0x0004:</tt> RESERVED */
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__IO uint32_t erase_all; /**< <tt>\b 0x0008:</tt> AES_ERASE_ALL Register - A write to this register will trigger AES Memory Erase */
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} mxc_aes_regs_t;
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/**
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* Structure type to access the AES Memory Registers.
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*/
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typedef struct {
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__IO uint32_t inp[4]; /**< <tt>\b 0x0000-0x000C:</tt> AES Input (128 bits) */
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__IO uint32_t key[8]; /**< <tt>\b 0x0010-0x002C:</tt> AES Symmetric Key (up to 256 bits) */
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__IO uint32_t out[4]; /**< <tt>\b 0x0030-0x003C:</tt> AES Output Data (128 bits) */
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__IO uint32_t expkey[8]; /**< <tt>\b 0x0040-0x005C:</tt> AES Expanded Key Data (256 bits) */
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} mxc_aes_mem_regs_t;
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/**@} end of group aes_registers */
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/**
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* @ingroup aes_registers
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* @defgroup AES_Register_Offsets Register Offsets
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* @brief AES Register Offsets from the AES Base Peripheral Address.
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* @{
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*/
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/**
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* AES Register offsets from the AES base peripheral address.
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*/
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#define MXC_R_AES_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0000</tt> */
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#define MXC_R_AES_OFFS_ERASE_ALL ((uint32_t)0x00000008UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0008</tt> */
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#define MXC_R_AES_MEM_OFFS_INP0 ((uint32_t)0x00000000UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0000</tt> */
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#define MXC_R_AES_MEM_OFFS_INP1 ((uint32_t)0x00000004UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0004</tt> */
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#define MXC_R_AES_MEM_OFFS_INP2 ((uint32_t)0x00000008UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0008</tt> */
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#define MXC_R_AES_MEM_OFFS_INP3 ((uint32_t)0x0000000CUL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x000C</tt> */
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#define MXC_R_AES_MEM_OFFS_KEY0 ((uint32_t)0x00000010UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0010</tt> */
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#define MXC_R_AES_MEM_OFFS_KEY1 ((uint32_t)0x00000014UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0014</tt> */
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#define MXC_R_AES_MEM_OFFS_KEY2 ((uint32_t)0x00000018UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0018</tt> */
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#define MXC_R_AES_MEM_OFFS_KEY3 ((uint32_t)0x0000001CUL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x001C</tt> */
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#define MXC_R_AES_MEM_OFFS_KEY4 ((uint32_t)0x00000020UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0020</tt> */
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#define MXC_R_AES_MEM_OFFS_KEY5 ((uint32_t)0x00000024UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0024</tt> */
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#define MXC_R_AES_MEM_OFFS_KEY6 ((uint32_t)0x00000028UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0028</tt> */
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#define MXC_R_AES_MEM_OFFS_KEY7 ((uint32_t)0x0000002CUL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x002C</tt> */
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#define MXC_R_AES_MEM_OFFS_OUT0 ((uint32_t)0x00000030UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0030</tt> */
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#define MXC_R_AES_MEM_OFFS_OUT1 ((uint32_t)0x00000034UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0034</tt> */
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#define MXC_R_AES_MEM_OFFS_OUT2 ((uint32_t)0x00000038UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0038</tt> */
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#define MXC_R_AES_MEM_OFFS_OUT3 ((uint32_t)0x0000003CUL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x003C</tt> */
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#define MXC_R_AES_MEM_OFFS_EXPKEY0 ((uint32_t)0x00000040UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0040</tt> */
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#define MXC_R_AES_MEM_OFFS_EXPKEY1 ((uint32_t)0x00000044UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0044</tt> */
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#define MXC_R_AES_MEM_OFFS_EXPKEY2 ((uint32_t)0x00000048UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0048</tt> */
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#define MXC_R_AES_MEM_OFFS_EXPKEY3 ((uint32_t)0x0000004CUL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x004C</tt> */
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#define MXC_R_AES_MEM_OFFS_EXPKEY4 ((uint32_t)0x00000050UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0050</tt> */
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#define MXC_R_AES_MEM_OFFS_EXPKEY5 ((uint32_t)0x00000054UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0054</tt> */
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#define MXC_R_AES_MEM_OFFS_EXPKEY6 ((uint32_t)0x00000058UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0058</tt> */
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#define MXC_R_AES_MEM_OFFS_EXPKEY7 ((uint32_t)0x0000005CUL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x005C</tt> */
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/**@} end of group AES_Register_Offsets */
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/**
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* @ingroup aes_registers
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* @defgroup AES_CTRL_Register AES_CTRL
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* @brief Field Positions and Bit Masks for the AES_CTRL register
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* @{
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*/
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#define MXC_F_AES_CTRL_START_POS 0 /**< AES_CTRL START Position */
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#define MXC_F_AES_CTRL_START ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_START_POS)) /**< AES_CTRL START Mask */
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#define MXC_F_AES_CTRL_CRYPT_MODE_POS 1 /**< AES_CTRL CRYPT_MODE Position */
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#define MXC_F_AES_CTRL_CRYPT_MODE ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_CRYPT_MODE_POS)) /**< AES_CTRL CRYPT_MODE Mask */
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#define MXC_F_AES_CTRL_EXP_KEY_MODE_POS 2 /**< AES_CTRL EXP_KEY_MODE Position */
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#define MXC_F_AES_CTRL_EXP_KEY_MODE ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_EXP_KEY_MODE_POS)) /**< AES_CTRL EXP_KEY_MODE Mask */
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#define MXC_F_AES_CTRL_KEY_SIZE_POS 3 /**< AES_CTRL KEY_SIZE Position */
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#define MXC_F_AES_CTRL_KEY_SIZE ((uint32_t)(0x00000003UL << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< AES_CTRL KEY_SIZE Mask */
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#define MXC_F_AES_CTRL_INTEN_POS 5 /**< AES_CTRL INTEN Position */
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#define MXC_F_AES_CTRL_INTEN ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTEN_POS)) /**< AES_CTRL INTEN Mask */
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#define MXC_F_AES_CTRL_INTFL_POS 6 /**< AES_CTRL INTFL Position */
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#define MXC_F_AES_CTRL_INTFL ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTFL_POS)) /**< AES_CTRL INTFL Mask */
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#define MXC_F_AES_CTRL_LOAD_HW_KEY_POS 7 /**< AES_CTRL LOAD_HW_KEY Position */
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#define MXC_F_AES_CTRL_LOAD_HW_KEY ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_LOAD_HW_KEY_POS)) /**< AES_CTRL LOAD_HW_KEY Mask */
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/**@} end of aes_registers group */
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/*
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Field values and shifted values for module AES.
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*/
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///@cond
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#define MXC_V_AES_CTRL_ENCRYPT_MODE ((uint32_t)(0x00000000UL)) /**< AES_CTRL: CRYPT_MODE Field: Encryption Mode value */
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#define MXC_V_AES_CTRL_DECRYPT_MODE ((uint32_t)(0x00000001UL)) /**< AES_CTRL: CRYPT_MODE Field: Decryption Mode value */
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#define MXC_S_AES_CTRL_ENCRYPT_MODE ((uint32_t)(MXC_V_AES_CTRL_ENCRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS)) /**< AES_CTRL: CRYPT_MODE Field: Encryption Mode Shifted Value*/
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#define MXC_S_AES_CTRL_DECRYPT_MODE ((uint32_t)(MXC_V_AES_CTRL_DECRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS)) /**< AES_CTRL: CRYPT_MODE Field: Decryption Mode Shifted Value*/
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#define MXC_V_AES_CTRL_CALC_NEW_EXP_KEY ((uint32_t)(0x00000000UL)) /**< AES_CTRL: EXP_KEY_MODE Field: Calculate New Exp Key value */
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#define MXC_V_AES_CTRL_USE_LAST_EXP_KEY ((uint32_t)(0x00000001UL)) /**< AES_CTRL: EXP_KEY_MODE Field: Use previous Exp Key value */
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#define MXC_S_AES_CTRL_CALC_NEW_EXP_KEY ((uint32_t)(MXC_V_AES_CTRL_CALC_NEW_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS)) /**< AES_CTRL: EXP_KEY_MODE Field: Calculate New Exp Key Shifted Value*/
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#define MXC_S_AES_CTRL_USE_LAST_EXP_KEY ((uint32_t)(MXC_V_AES_CTRL_USE_LAST_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS)) /**< AES_CTRL: EXP_KEY_MODE Field: Use previous Exp Key Shifted Value*/
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#define MXC_V_AES_CTRL_KEY_SIZE_128 ((uint32_t)(0x00000000UL)) /**< AES_CTRL: KEY_SIZE 128-bit setting value */
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#define MXC_V_AES_CTRL_KEY_SIZE_192 ((uint32_t)(0x00000001UL)) /**< AES_CTRL: KEY_SIZE 192-bit setting value */
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#define MXC_V_AES_CTRL_KEY_SIZE_256 ((uint32_t)(0x00000002UL)) /**< AES_CTRL: KEY_SIZE 256-bit setting value */
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#define MXC_S_AES_CTRL_KEY_SIZE_128 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_128 << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< AES_CTRL: KEY_SIZE 128-bit Shifted Value */
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#define MXC_S_AES_CTRL_KEY_SIZE_192 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_192 << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< AES_CTRL: KEY_SIZE 192-bit Shifted Value */
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#define MXC_S_AES_CTRL_KEY_SIZE_256 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_256 << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< AES_CTRL: KEY_SIZE 256-bit Shifted Value */
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///@endcond
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#ifdef __cplusplus
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}
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#endif
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#endif /* _MXC_AES_REGS_H_ */
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