mirror of https://github.com/ARMmbed/mbed-os.git
680 lines
21 KiB
C
680 lines
21 KiB
C
/**************************************************************************//**
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* @file cmsis_gcc.h
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* @brief CMSIS compiler specific macros, functions, instructions
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* @version V1.0.2
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* @date 09. April 2018
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******************************************************************************/
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/*
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* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __CMSIS_GCC_H
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#define __CMSIS_GCC_H
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/* ignore some GCC warnings */
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#pragma GCC diagnostic push
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#pragma GCC diagnostic ignored "-Wsign-conversion"
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#pragma GCC diagnostic ignored "-Wconversion"
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#pragma GCC diagnostic ignored "-Wunused-parameter"
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/* Fallback for __has_builtin */
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#ifndef __has_builtin
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#define __has_builtin(x) (0)
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#endif
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/* CMSIS compiler specific defines */
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#ifndef __ASM
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#define __ASM asm
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#endif
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#ifndef __INLINE
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#define __INLINE inline
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#endif
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#ifndef __FORCEINLINE
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#define __FORCEINLINE __attribute__((always_inline))
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#endif
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#ifndef __STATIC_INLINE
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#define __STATIC_INLINE static inline
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#endif
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#ifndef __STATIC_FORCEINLINE
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#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
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#endif
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#ifndef __NO_RETURN
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#define __NO_RETURN __attribute__((__noreturn__))
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#endif
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#ifndef CMSIS_DEPRECATED
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#define CMSIS_DEPRECATED __attribute__((deprecated))
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#endif
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#ifndef __USED
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#define __USED __attribute__((used))
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#endif
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#ifndef __WEAK
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#define __WEAK __attribute__((weak))
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#endif
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#ifndef __PACKED
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#define __PACKED __attribute__((packed, aligned(1)))
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#endif
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#ifndef __PACKED_STRUCT
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#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
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#endif
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#ifndef __UNALIGNED_UINT16_WRITE
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#pragma GCC diagnostic push
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#pragma GCC diagnostic ignored "-Wpacked"
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/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
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__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
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#pragma GCC diagnostic pop
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#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
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#endif
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#ifndef __UNALIGNED_UINT16_READ
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#pragma GCC diagnostic push
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#pragma GCC diagnostic ignored "-Wpacked"
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/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
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__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
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#pragma GCC diagnostic pop
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#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
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#endif
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#ifndef __UNALIGNED_UINT32_WRITE
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#pragma GCC diagnostic push
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#pragma GCC diagnostic ignored "-Wpacked"
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/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
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__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
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#pragma GCC diagnostic pop
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#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
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#endif
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#ifndef __UNALIGNED_UINT32_READ
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#pragma GCC diagnostic push
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#pragma GCC diagnostic ignored "-Wpacked"
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__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
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#pragma GCC diagnostic pop
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#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
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#endif
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#ifndef __ALIGNED
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#define __ALIGNED(x) __attribute__((aligned(x)))
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#endif
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/* ########################## Core Instruction Access ######################### */
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/**
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\brief No Operation
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*/
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#define __NOP() __ASM volatile ("nop")
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/**
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\brief Wait For Interrupt
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*/
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#define __WFI() __ASM volatile ("wfi")
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/**
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\brief Wait For Event
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*/
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#define __WFE() __ASM volatile ("wfe")
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/**
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\brief Send Event
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*/
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#define __SEV() __ASM volatile ("sev")
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/**
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\brief Instruction Synchronization Barrier
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\details Instruction Synchronization Barrier flushes the pipeline in the processor,
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so that all instructions following the ISB are fetched from cache or memory,
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after the instruction has been completed.
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*/
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__STATIC_FORCEINLINE void __ISB(void)
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{
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__ASM volatile ("isb 0xF":::"memory");
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}
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/**
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\brief Data Synchronization Barrier
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\details Acts as a special kind of Data Memory Barrier.
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It completes when all explicit memory accesses before this instruction complete.
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*/
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__STATIC_FORCEINLINE void __DSB(void)
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{
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__ASM volatile ("dsb 0xF":::"memory");
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}
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/**
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\brief Data Memory Barrier
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\details Ensures the apparent order of the explicit memory operations before
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and after the instruction, without ensuring their completion.
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*/
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__STATIC_FORCEINLINE void __DMB(void)
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{
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__ASM volatile ("dmb 0xF":::"memory");
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}
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/**
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\brief Reverse byte order (32 bit)
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\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
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{
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#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
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return __builtin_bswap32(value);
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#else
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uint32_t result;
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__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
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return result;
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#endif
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}
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/**
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\brief Reverse byte order (16 bit)
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\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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#ifndef __NO_EMBEDDED_ASM
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__attribute__((section(".rev16_text"))) __STATIC_INLINE uint32_t __REV16(uint32_t value)
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{
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uint32_t result;
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__ASM volatile("rev16 %0, %1" : "=r" (result) : "r" (value));
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return result;
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}
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#endif
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/**
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\brief Reverse byte order (16 bit)
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\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
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{
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#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
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return (int16_t)__builtin_bswap16(value);
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#else
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int16_t result;
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__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
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return result;
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#endif
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}
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/**
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\brief Rotate Right in unsigned value (32 bit)
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\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
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\param [in] op1 Value to rotate
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\param [in] op2 Number of Bits to rotate
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\return Rotated value
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*/
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__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
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{
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op2 %= 32U;
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if (op2 == 0U) {
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return op1;
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}
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return (op1 >> op2) | (op1 << (32U - op2));
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}
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/**
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\brief Breakpoint
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\param [in] value is ignored by the processor.
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If required, a debugger can use it to store additional information about the breakpoint.
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*/
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#define __BKPT(value) __ASM volatile ("bkpt "#value)
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/**
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\brief Reverse bit order of value
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\details Reverses the bit order of the given value.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
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{
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uint32_t result;
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#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
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(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
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(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
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__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
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#else
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int32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
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result = value; /* r will be reversed bits of v; first get LSB of v */
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for (value >>= 1U; value; value >>= 1U)
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{
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result <<= 1U;
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result |= value & 1U;
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s--;
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}
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result <<= s; /* shift when v's highest bits are zero */
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#endif
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return result;
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}
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/**
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\brief Count leading zeros
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\param [in] value Value to count the leading zeros
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\return number of leading zeros in value
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*/
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#define __CLZ (uint8_t)__builtin_clz
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/**
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\brief LDR Exclusive (8 bit)
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\details Executes a exclusive LDR instruction for 8 bit value.
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\param [in] ptr Pointer to data
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\return value of type uint8_t at (*ptr)
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*/
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__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
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{
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uint32_t result;
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#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
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__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
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#else
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/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
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accepted by assembler. So has to use following less efficient pattern.
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*/
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__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
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#endif
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return ((uint8_t) result); /* Add explicit type cast here */
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}
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/**
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\brief LDR Exclusive (16 bit)
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\details Executes a exclusive LDR instruction for 16 bit values.
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\param [in] ptr Pointer to data
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\return value of type uint16_t at (*ptr)
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*/
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__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
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{
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uint32_t result;
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#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
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__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
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#else
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/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
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accepted by assembler. So has to use following less efficient pattern.
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*/
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__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
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#endif
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return ((uint16_t) result); /* Add explicit type cast here */
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}
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/**
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\brief LDR Exclusive (32 bit)
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\details Executes a exclusive LDR instruction for 32 bit values.
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\param [in] ptr Pointer to data
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\return value of type uint32_t at (*ptr)
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*/
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__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
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{
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uint32_t result;
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__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
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return(result);
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}
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/**
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\brief STR Exclusive (8 bit)
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\details Executes a exclusive STR instruction for 8 bit values.
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\param [in] value Value to store
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\param [in] ptr Pointer to location
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\return 0 Function succeeded
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\return 1 Function failed
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*/
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__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
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{
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uint32_t result;
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__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
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return(result);
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}
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/**
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\brief STR Exclusive (16 bit)
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\details Executes a exclusive STR instruction for 16 bit values.
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\param [in] value Value to store
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\param [in] ptr Pointer to location
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\return 0 Function succeeded
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\return 1 Function failed
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*/
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__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
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{
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uint32_t result;
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__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
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return(result);
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}
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/**
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\brief STR Exclusive (32 bit)
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\details Executes a exclusive STR instruction for 32 bit values.
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\param [in] value Value to store
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\param [in] ptr Pointer to location
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\return 0 Function succeeded
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\return 1 Function failed
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*/
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__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
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{
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uint32_t result;
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__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
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return(result);
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}
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/**
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\brief Remove the exclusive lock
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\details Removes the exclusive lock which is created by LDREX.
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*/
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__STATIC_FORCEINLINE void __CLREX(void)
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{
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__ASM volatile ("clrex" ::: "memory");
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}
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/**
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\brief Signed Saturate
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\details Saturates a signed value.
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\param [in] value Value to be saturated
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\param [in] sat Bit position to saturate to (1..32)
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\return Saturated value
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*/
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#define __SSAT(ARG1,ARG2) \
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__extension__ \
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({ \
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int32_t __RES, __ARG1 = (ARG1); \
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__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
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__RES; \
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})
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/**
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\brief Unsigned Saturate
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\details Saturates an unsigned value.
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\param [in] value Value to be saturated
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\param [in] sat Bit position to saturate to (0..31)
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\return Saturated value
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*/
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#define __USAT(ARG1,ARG2) \
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__extension__ \
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({ \
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uint32_t __RES, __ARG1 = (ARG1); \
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__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
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__RES; \
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})
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/* ########################### Core Function Access ########################### */
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/**
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\brief Enable IRQ Interrupts
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\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
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Can only be executed in Privileged modes.
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*/
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__STATIC_FORCEINLINE void __enable_irq(void)
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{
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__ASM volatile ("cpsie i" : : : "memory");
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}
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/**
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\brief Disable IRQ Interrupts
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\details Disables IRQ interrupts by setting the I-bit in the CPSR.
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Can only be executed in Privileged modes.
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*/
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__STATIC_FORCEINLINE void __disable_irq(void)
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{
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__ASM volatile ("cpsid i" : : : "memory");
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}
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/**
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\brief Get FPSCR
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\details Returns the current value of the Floating Point Status/Control register.
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\return Floating Point Status/Control register value
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*/
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__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
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{
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#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
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(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
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#if __has_builtin(__builtin_arm_get_fpscr)
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// Re-enable using built-in when GCC has been fixed
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// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
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/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
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return __builtin_arm_get_fpscr();
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#else
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uint32_t result;
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__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
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return(result);
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#endif
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#else
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return(0U);
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#endif
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}
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/**
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\brief Set FPSCR
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\details Assigns the given value to the Floating Point Status/Control register.
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\param [in] fpscr Floating Point Status/Control value to set
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*/
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__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
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{
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#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
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(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
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#if __has_builtin(__builtin_arm_set_fpscr)
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// Re-enable using built-in when GCC has been fixed
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// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
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/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
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__builtin_arm_set_fpscr(fpscr);
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#else
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__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
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#endif
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#else
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(void)fpscr;
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#endif
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}
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/** \brief Get CPSR Register
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\return CPSR Register value
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*/
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__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
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{
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uint32_t result;
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__ASM volatile("MRS %0, cpsr" : "=r" (result) );
|
|
return(result);
|
|
}
|
|
|
|
/** \brief Set CPSR Register
|
|
\param [in] cpsr CPSR value to set
|
|
*/
|
|
__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
|
|
{
|
|
__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
|
|
}
|
|
|
|
/** \brief Get Mode
|
|
\return Processor Mode
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t __get_mode(void)
|
|
{
|
|
return (__get_CPSR() & 0x1FU);
|
|
}
|
|
|
|
/** \brief Set Mode
|
|
\param [in] mode Mode value to set
|
|
*/
|
|
__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
|
|
{
|
|
__ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
|
|
}
|
|
|
|
/** \brief Get Stack Pointer
|
|
\return Stack Pointer value
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t __get_SP(void)
|
|
{
|
|
uint32_t result;
|
|
__ASM volatile("MOV %0, sp" : "=r" (result) : : "memory");
|
|
return result;
|
|
}
|
|
|
|
/** \brief Set Stack Pointer
|
|
\param [in] stack Stack Pointer value to set
|
|
*/
|
|
__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
|
|
{
|
|
__ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
|
|
}
|
|
|
|
/** \brief Get USR/SYS Stack Pointer
|
|
\return USR/SYS Stack Pointer value
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
|
|
{
|
|
uint32_t cpsr = __get_CPSR();
|
|
uint32_t result;
|
|
__ASM volatile(
|
|
"CPS #0x1F \n"
|
|
"MOV %0, sp " : "=r"(result) : : "memory"
|
|
);
|
|
__set_CPSR(cpsr);
|
|
__ISB();
|
|
return result;
|
|
}
|
|
|
|
/** \brief Set USR/SYS Stack Pointer
|
|
\param [in] topOfProcStack USR/SYS Stack Pointer value to set
|
|
*/
|
|
__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
|
|
{
|
|
uint32_t cpsr = __get_CPSR();
|
|
__ASM volatile(
|
|
"CPS #0x1F \n"
|
|
"MOV sp, %0 " : : "r" (topOfProcStack) : "memory"
|
|
);
|
|
__set_CPSR(cpsr);
|
|
__ISB();
|
|
}
|
|
|
|
/** \brief Get FPEXC
|
|
\return Floating Point Exception Control register value
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
|
|
{
|
|
#if (__FPU_PRESENT == 1)
|
|
uint32_t result;
|
|
__ASM volatile("VMRS %0, fpexc" : "=r" (result) );
|
|
return(result);
|
|
#else
|
|
return(0);
|
|
#endif
|
|
}
|
|
|
|
/** \brief Set FPEXC
|
|
\param [in] fpexc Floating Point Exception Control value to set
|
|
*/
|
|
__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
|
|
{
|
|
#if (__FPU_PRESENT == 1)
|
|
__ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* Include common core functions to access Coprocessor 15 registers
|
|
*/
|
|
|
|
#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
|
|
#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
|
|
#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
|
|
#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
|
|
|
|
#include "cmsis_cp15.h"
|
|
|
|
/** \brief Enable Floating Point Unit
|
|
|
|
Critical section, called from undef handler, so systick is disabled
|
|
*/
|
|
__STATIC_INLINE void __FPU_Enable(void)
|
|
{
|
|
__ASM volatile(
|
|
//Permit access to VFP/NEON, registers by modifying CPACR
|
|
" MRC p15,0,R1,c1,c0,2 \n"
|
|
" ORR R1,R1,#0x00F00000 \n"
|
|
" MCR p15,0,R1,c1,c0,2 \n"
|
|
|
|
//Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
|
|
" ISB \n"
|
|
|
|
//Enable VFP/NEON
|
|
" VMRS R1,FPEXC \n"
|
|
" ORR R1,R1,#0x40000000 \n"
|
|
" VMSR FPEXC,R1 \n"
|
|
|
|
//Initialise VFP/NEON registers to 0
|
|
" MOV R2,#0 \n"
|
|
|
|
//Initialise D16 registers to 0
|
|
" VMOV D0, R2,R2 \n"
|
|
" VMOV D1, R2,R2 \n"
|
|
" VMOV D2, R2,R2 \n"
|
|
" VMOV D3, R2,R2 \n"
|
|
" VMOV D4, R2,R2 \n"
|
|
" VMOV D5, R2,R2 \n"
|
|
" VMOV D6, R2,R2 \n"
|
|
" VMOV D7, R2,R2 \n"
|
|
" VMOV D8, R2,R2 \n"
|
|
" VMOV D9, R2,R2 \n"
|
|
" VMOV D10,R2,R2 \n"
|
|
" VMOV D11,R2,R2 \n"
|
|
" VMOV D12,R2,R2 \n"
|
|
" VMOV D13,R2,R2 \n"
|
|
" VMOV D14,R2,R2 \n"
|
|
" VMOV D15,R2,R2 \n"
|
|
|
|
#if (defined(__ARM_NEON) && (__ARM_NEON == 1))
|
|
//Initialise D32 registers to 0
|
|
" VMOV D16,R2,R2 \n"
|
|
" VMOV D17,R2,R2 \n"
|
|
" VMOV D18,R2,R2 \n"
|
|
" VMOV D19,R2,R2 \n"
|
|
" VMOV D20,R2,R2 \n"
|
|
" VMOV D21,R2,R2 \n"
|
|
" VMOV D22,R2,R2 \n"
|
|
" VMOV D23,R2,R2 \n"
|
|
" VMOV D24,R2,R2 \n"
|
|
" VMOV D25,R2,R2 \n"
|
|
" VMOV D26,R2,R2 \n"
|
|
" VMOV D27,R2,R2 \n"
|
|
" VMOV D28,R2,R2 \n"
|
|
" VMOV D29,R2,R2 \n"
|
|
" VMOV D30,R2,R2 \n"
|
|
" VMOV D31,R2,R2 \n"
|
|
#endif
|
|
|
|
//Initialise FPSCR to a known state
|
|
" VMRS R2,FPSCR \n"
|
|
" LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
|
|
" AND R2,R2,R3 \n"
|
|
" VMSR FPSCR,R2 "
|
|
);
|
|
}
|
|
|
|
#pragma GCC diagnostic pop
|
|
|
|
#endif /* __CMSIS_GCC_H */
|