mirror of https://github.com/ARMmbed/mbed-os.git
151 lines
6.1 KiB
C
151 lines
6.1 KiB
C
/*******************************************************************************
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* Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
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* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Except as contained in this notice, the name of Maxim Integrated
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* Products, Inc. shall not be used except as stated in the Maxim Integrated
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* Products, Inc. Branding Policy.
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*
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* The mere transfer of this software does not imply any licenses
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* of trade secrets, proprietary technology, copyrights, patents,
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* trademarks, maskwork rights, or any other form of intellectual
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* property whatsoever. Maxim Integrated Products, Inc. retains all
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* ownership rights.
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*******************************************************************************
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*/
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#ifndef _MXC_WDT_REGS_H_
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#define _MXC_WDT_REGS_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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/**
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* @file wdt_regs.h
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* @addtogroup wdt WDT
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* @{
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*/
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/**
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* @brief Defines watchdog timer periods
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*/
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typedef enum {
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/** 2^31 cycle period */
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MXC_E_WDT_PERIOD_2_31_CLKS = 0,
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/** 2^30 cycle period */
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MXC_E_WDT_PERIOD_2_30_CLKS,
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/** 2^29 cycle period */
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MXC_E_WDT_PERIOD_2_29_CLKS,
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/** 2^28 cycle period */
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MXC_E_WDT_PERIOD_2_28_CLKS,
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/** 2^27 cycle period */
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MXC_E_WDT_PERIOD_2_27_CLKS,
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/** 2^26 cycle period */
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MXC_E_WDT_PERIOD_2_26_CLKS,
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/** 2^25 cycle period */
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MXC_E_WDT_PERIOD_2_25_CLKS,
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/** 2^24 cycle period */
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MXC_E_WDT_PERIOD_2_24_CLKS,
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/** 2^23 cycle period */
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MXC_E_WDT_PERIOD_2_23_CLKS,
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/** 2^22 cycle period */
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MXC_E_WDT_PERIOD_2_22_CLKS,
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/** 2^21 cycle period */
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MXC_E_WDT_PERIOD_2_21_CLKS,
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/** 2^20 cycle period */
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MXC_E_WDT_PERIOD_2_20_CLKS,
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/** 2^19 cycle period */
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MXC_E_WDT_PERIOD_2_19_CLKS,
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/** 2^18 cycle period */
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MXC_E_WDT_PERIOD_2_18_CLKS,
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/** 2^17 cycle period */
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MXC_E_WDT_PERIOD_2_17_CLKS,
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/** 2^16 cycle period */
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MXC_E_WDT_PERIOD_2_16_CLKS,
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} mxc_wdt_period_t;
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/* Offset Register Description
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====== ================================================ */
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typedef struct {
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__IO uint32_t ctrl; /* 0x0000 Watchdog Timer Control Register */
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__IO uint32_t clear; /* 0x0004 Watchdog Clear Register (Feed Dog) */
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__IO uint32_t int_rst_fl; /* 0x0008 Watchdog Interrupt/Reset Flags */
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__IO uint32_t int_rst_en; /* 0x000C Interrupt/Reset Enable/Disable Controls */
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__I uint32_t rsv0010; /* 0x0010 */
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__IO uint32_t lock_ctrl; /* 0x0014 Lock Register Setting for WDT CTRL */
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} mxc_wdt_regs_t;
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/*
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Register offsets for module WDT.
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*/
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#define MXC_R_WDT_OFFS_CTRL ((uint32_t)0x00000000UL)
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#define MXC_R_WDT_OFFS_CLEAR ((uint32_t)0x00000004UL)
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#define MXC_R_WDT_OFFS_INT_RST_FL ((uint32_t)0x00000008UL)
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#define MXC_R_WDT_OFFS_INT_RST_EN ((uint32_t)0x0000000CUL)
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#define MXC_R_WDT_OFFS_LOCK_CTRL ((uint32_t)0x00000014UL)
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#define MXC_V_WDT_WDLOCK_LOCK_KEY ((uint8_t)0x24)
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#define MXC_V_WDT_WDLOCK_UNLOCK_KEY ((uint8_t)0x42)
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/*
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Field positions and masks for module WDT.
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*/
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#define MXC_F_WDT_CTRL_INT_PERIOD_POS 0
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#define MXC_F_WDT_CTRL_INT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_INT_PERIOD_POS))
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#define MXC_F_WDT_CTRL_RST_PERIOD_POS 4
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#define MXC_F_WDT_CTRL_RST_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_RST_PERIOD_POS))
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#define MXC_F_WDT_CTRL_EN_TIMER_POS 8
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#define MXC_F_WDT_CTRL_EN_TIMER ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_TIMER_POS))
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#define MXC_F_WDT_CTRL_EN_CLOCK_POS 9
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#define MXC_F_WDT_CTRL_EN_CLOCK ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_CLOCK_POS))
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#define MXC_F_WDT_CTRL_WAIT_PERIOD_POS 12
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#define MXC_F_WDT_CTRL_WAIT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
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#define MXC_F_WDT_FLAGS_TIMEOUT_POS 0
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#define MXC_F_WDT_FLAGS_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_TIMEOUT_POS))
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#define MXC_F_WDT_FLAGS_PRE_WIN_POS 1
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#define MXC_F_WDT_FLAGS_PRE_WIN ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_PRE_WIN_POS))
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#define MXC_F_WDT_FLAGS_RESET_OUT_POS 2
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#define MXC_F_WDT_FLAGS_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_RESET_OUT_POS))
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#define MXC_F_WDT_ENABLE_TIMEOUT_POS 0
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#define MXC_F_WDT_ENABLE_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_TIMEOUT_POS))
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#define MXC_F_WDT_ENABLE_PRE_WIN_POS 1
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#define MXC_F_WDT_ENABLE_PRE_WIN ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_PRE_WIN_POS))
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#define MXC_F_WDT_ENABLE_RESET_OUT_POS 2
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#define MXC_F_WDT_ENABLE_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_RESET_OUT_POS))
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#define MXC_F_WDT_LOCK_CTRL_WDLOCK_POS 0
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#define MXC_F_WDT_LOCK_CTRL_WDLOCK ((uint32_t)(0x000000FFUL << MXC_F_WDT_LOCK_CTRL_WDLOCK_POS))
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#ifdef __cplusplus
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}
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#endif
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/**
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* @}
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*/
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#endif /* _MXC_WDT_REGS_H_ */
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