mirror of https://github.com/ARMmbed/mbed-os.git
160 lines
7.8 KiB
C
160 lines
7.8 KiB
C
/*******************************************************************************
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* Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
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* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Except as contained in this notice, the name of Maxim Integrated
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* Products, Inc. shall not be used except as stated in the Maxim Integrated
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* Products, Inc. Branding Policy.
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*
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* The mere transfer of this software does not imply any licenses
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* of trade secrets, proprietary technology, copyrights, patents,
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* trademarks, maskwork rights, or any other form of intellectual
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* property whatsoever. Maxim Integrated Products, Inc. retains all
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* ownership rights.
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*******************************************************************************
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*/
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#ifndef _MXC_AES_REGS_H_
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#define _MXC_AES_REGS_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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/**
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* @file aes_regs.h
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* @addtogroup aes AES
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* @{
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*/
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/**
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* @brief Settings for AES_CTRL.CRYPT_MODE
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*/
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typedef enum {
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MXC_E_AES_CTRL_ENCRYPT_MODE = 0,
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MXC_E_AES_CTRL_DECRYPT_MODE = 1
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} mxc_aes_ctrl_crypt_mode_t;
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/**
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* @brief Settings for AES_CTRL.EXP_KEY_MODE
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*/
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typedef enum {
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MXC_E_AES_CTRL_CALC_NEW_EXP_KEY = 0,
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MXC_E_AES_CTRL_USE_LAST_EXP_KEY = 1
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} mxc_aes_ctrl_exp_key_mode_t;
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/**
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* @brief Settings for AES_CTRL.KEY_SIZE
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*/
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typedef enum {
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MXC_E_AES_CTRL_KEY_SIZE_128 = 0,
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MXC_E_AES_CTRL_KEY_SIZE_192 = 1,
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MXC_E_AES_CTRL_KEY_SIZE_256 = 2
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} mxc_aes_ctrl_key_size_t;
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/* Offset Register Description
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====== =========================================================== */
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typedef struct {
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__IO uint32_t ctrl; /* 0x0000 AES Control and Status */
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__I uint32_t rsv004; /* 0x0004 */
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__IO uint32_t erase_all; /* 0x0008 Write to Trigger AES Memory Erase */
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} mxc_aes_regs_t;
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/* Offset Register Description
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====== =========================================================== */
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typedef struct {
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__IO uint32_t inp[4]; /* 0x0000 AES Input 0..3 */
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__IO uint32_t key[8]; /* 0x0010 AES Key 0..7 */
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__IO uint32_t out[4]; /* 0x0030 AES Output 0..3 */
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__IO uint32_t expkey[8]; /* 0x0040 AES Expanded Key Data 0..7 */
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} mxc_aes_mem_regs_t;
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/*
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Register offsets for module AES.
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*/
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#define MXC_R_AES_OFFS_CTRL ((uint32_t)0x00000000UL)
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#define MXC_R_AES_OFFS_ERASE_ALL ((uint32_t)0x00000008UL)
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#define MXC_R_AES_MEM_OFFS_INP0 ((uint32_t)0x00000000UL)
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#define MXC_R_AES_MEM_OFFS_INP1 ((uint32_t)0x00000004UL)
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#define MXC_R_AES_MEM_OFFS_INP2 ((uint32_t)0x00000008UL)
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#define MXC_R_AES_MEM_OFFS_INP3 ((uint32_t)0x0000000CUL)
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#define MXC_R_AES_MEM_OFFS_KEY0 ((uint32_t)0x00000010UL)
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#define MXC_R_AES_MEM_OFFS_KEY1 ((uint32_t)0x00000014UL)
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#define MXC_R_AES_MEM_OFFS_KEY2 ((uint32_t)0x00000018UL)
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#define MXC_R_AES_MEM_OFFS_KEY3 ((uint32_t)0x0000001CUL)
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#define MXC_R_AES_MEM_OFFS_KEY4 ((uint32_t)0x00000020UL)
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#define MXC_R_AES_MEM_OFFS_KEY5 ((uint32_t)0x00000024UL)
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#define MXC_R_AES_MEM_OFFS_KEY6 ((uint32_t)0x00000028UL)
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#define MXC_R_AES_MEM_OFFS_KEY7 ((uint32_t)0x0000002CUL)
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#define MXC_R_AES_MEM_OFFS_OUT0 ((uint32_t)0x00000030UL)
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#define MXC_R_AES_MEM_OFFS_OUT1 ((uint32_t)0x00000034UL)
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#define MXC_R_AES_MEM_OFFS_OUT2 ((uint32_t)0x00000038UL)
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#define MXC_R_AES_MEM_OFFS_OUT3 ((uint32_t)0x0000003CUL)
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#define MXC_R_AES_MEM_OFFS_EXPKEY0 ((uint32_t)0x00000040UL)
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#define MXC_R_AES_MEM_OFFS_EXPKEY1 ((uint32_t)0x00000044UL)
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#define MXC_R_AES_MEM_OFFS_EXPKEY2 ((uint32_t)0x00000048UL)
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#define MXC_R_AES_MEM_OFFS_EXPKEY3 ((uint32_t)0x0000004CUL)
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#define MXC_R_AES_MEM_OFFS_EXPKEY4 ((uint32_t)0x00000050UL)
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#define MXC_R_AES_MEM_OFFS_EXPKEY5 ((uint32_t)0x00000054UL)
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#define MXC_R_AES_MEM_OFFS_EXPKEY6 ((uint32_t)0x00000058UL)
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#define MXC_R_AES_MEM_OFFS_EXPKEY7 ((uint32_t)0x0000005CUL)
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#define MXC_F_AES_CTRL_START_POS 0
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#define MXC_F_AES_CTRL_START ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_START_POS))
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#define MXC_F_AES_CTRL_CRYPT_MODE_POS 1
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#define MXC_F_AES_CTRL_CRYPT_MODE ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_CRYPT_MODE_POS))
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#define MXC_F_AES_CTRL_EXP_KEY_MODE_POS 2
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#define MXC_F_AES_CTRL_EXP_KEY_MODE ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_EXP_KEY_MODE_POS))
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#define MXC_F_AES_CTRL_KEY_SIZE_POS 3
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#define MXC_F_AES_CTRL_KEY_SIZE ((uint32_t)(0x00000003UL << MXC_F_AES_CTRL_KEY_SIZE_POS))
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#define MXC_F_AES_CTRL_INTEN_POS 5
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#define MXC_F_AES_CTRL_INTEN ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTEN_POS))
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#define MXC_F_AES_CTRL_INTFL_POS 6
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#define MXC_F_AES_CTRL_INTFL ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTFL_POS))
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#define MXC_V_AES_CTRL_ENCRYPT_MODE 0
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#define MXC_V_AES_CTRL_DECRYPT_MODE 1
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#define MXC_S_AES_CTRL_ENCRYPT_MODE ((uint32_t)(MXC_V_AES_CTRL_ENCRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS))
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#define MXC_S_AES_CTRL_DECRYPT_MODE ((uint32_t)(MXC_V_AES_CTRL_DECRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS))
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#define MXC_V_AES_CTRL_CALC_NEW_EXP_KEY 0
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#define MXC_V_AES_CTRL_USE_LAST_EXP_KEY 1
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#define MXC_S_AES_CTRL_CALC_NEW_EXP_KEY ((uint32_t)(MXC_V_AES_CTRL_CALC_NEW_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS))
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#define MXC_S_AES_CTRL_USE_LAST_EXP_KEY ((uint32_t)(MXC_V_AES_CTRL_USE_LAST_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS))
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#define MXC_V_AES_CTRL_KEY_SIZE_128 0
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#define MXC_V_AES_CTRL_KEY_SIZE_192 1
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#define MXC_V_AES_CTRL_KEY_SIZE_256 2
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#define MXC_S_AES_CTRL_KEY_SIZE_128 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_128 << MXC_F_AES_CTRL_KEY_SIZE_POS))
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#define MXC_S_AES_CTRL_KEY_SIZE_192 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_192 << MXC_F_AES_CTRL_KEY_SIZE_POS))
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#define MXC_S_AES_CTRL_KEY_SIZE_256 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_256 << MXC_F_AES_CTRL_KEY_SIZE_POS))
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#ifdef __cplusplus
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}
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#endif
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/**
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* @}
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*/
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#endif /* _MXC_AES_REGS_H_ */
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