mirror of https://github.com/ARMmbed/mbed-os.git
203 lines
6.4 KiB
C
203 lines
6.4 KiB
C
/* mbed Microcontroller Library
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*******************************************************************************
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* Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of ARM Limited nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************
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*/
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#include "mbed_assert.h"
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#include <math.h>
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#include "spi_api.h"
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#include "cmsis.h"
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#include "pinmap.h"
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#include "mbed_error.h"
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#include "PeripheralPins.h"
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static inline int ssp_disable(spi_t *obj);
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static inline int ssp_enable(spi_t *obj);
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void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
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// determine the SPI to use
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SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
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SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
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SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
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SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
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SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
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SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
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obj->spi = (SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
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MBED_ASSERT((int)obj->spi != NC);
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// enable power and clocking
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switch ((int)obj->spi) {
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case SPI_0: CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_MCLK; break; //PLL output clock
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case SPI_1: CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_MCLK; break;
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}
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// set default format and frequency
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if (ssel == NC) {
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spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
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} else {
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spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
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}
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spi_frequency(obj, 1000000);
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// enable the ssp channel
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ssp_enable(obj);
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// pin out the spi pins
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pinmap_pinout(mosi, PinMap_SPI_MOSI);
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pinmap_pinout(miso, PinMap_SPI_MISO);
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pinmap_pinout(sclk, PinMap_SPI_SCLK);
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if (ssel != NC) {
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pinmap_pinout(ssel, PinMap_SPI_SSEL);
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}
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}
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void spi_free(spi_t *obj) {}
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void spi_format(spi_t *obj, int bits, int mode, int slave) {
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ssp_disable(obj);
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MBED_ASSERT(((bits >= 4) && (bits <= 16)) && (mode >= 0 && mode <= 3));
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int polarity = (mode & 0x2) ? 1 : 0;
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int phase = (mode & 0x1) ? 1 : 0;
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// set it up
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int DSS = bits - 1; // DSS (data select size)
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int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
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int SPH = (phase) ? 1 : 0; // SPH - clock out phase
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int FRF = 0; // FRF (frame format) = SPI
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uint32_t tmp = obj->spi->CR0;
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tmp &= ~(0xFFFF);
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tmp |= DSS << 0
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| FRF << 4
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| SPO << 6
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| SPH << 7;
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obj->spi->CR0 = tmp;
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tmp = obj->spi->CR1;
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tmp &= ~(0xD);
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tmp |= 0 << 0 // LBM - loop back mode - off
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| ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
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| 0 << 3; // SOD - slave output disable - na
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obj->spi->CR1 = tmp;
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ssp_enable(obj);
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}
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void spi_frequency(spi_t *obj, int hz) {
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ssp_disable(obj);
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// setup the spi clock diveder to /1
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switch ((int)obj->spi) {
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case SPI_0:
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CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV1; //1/1 (bypass)
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break;
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case SPI_1:
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CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV1; //1/1 (bypass)
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break;
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}
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uint32_t HCLK = SystemCoreClock;
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int prescaler;
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for (prescaler = 2; prescaler <= 254; prescaler += 2) {
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int prescale_hz = HCLK / prescaler;
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// calculate the divider
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int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
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// check we can support the divider
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if (divider < 256) {
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// prescaler
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obj->spi->CPSR = prescaler;
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// divider
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obj->spi->CR0 &= ~(0xFFFF << 8);
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obj->spi->CR0 |= (divider - 1) << 8;
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ssp_enable(obj);
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return;
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}
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}
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error("Couldn't setup requested SPI frequency");
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}
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static inline int ssp_disable(spi_t *obj) {
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return obj->spi->CR1 &= ~(1 << 1);
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}
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static inline int ssp_enable(spi_t *obj) {
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return obj->spi->CR1 |= (1 << 1);
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}
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static inline int ssp_readable(spi_t *obj) {
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return obj->spi->SR & (1 << 2);
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}
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static inline int ssp_writeable(spi_t *obj) {
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return obj->spi->SR & (1 << 1);
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}
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static inline void ssp_write(spi_t *obj, int value) {
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while (!ssp_writeable(obj));
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obj->spi->DR = value;
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}
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static inline int ssp_read(spi_t *obj) {
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while (!ssp_readable(obj));
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return obj->spi->DR;
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}
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static inline int ssp_busy(spi_t *obj) {
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return (obj->spi->SR & (1 << 4)) ? (1) : (0);
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}
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int spi_master_write(spi_t *obj, int value) {
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ssp_write(obj, value);
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return ssp_read(obj);
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}
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int spi_slave_receive(spi_t *obj) {
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return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
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}
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int spi_slave_read(spi_t *obj) {
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return obj->spi->DR;
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}
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void spi_slave_write(spi_t *obj, int value) {
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while (ssp_writeable(obj) == 0) ;
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obj->spi->DR = value;
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}
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int spi_busy(spi_t *obj) {
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return ssp_busy(obj);
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}
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