mirror of https://github.com/ARMmbed/mbed-os.git
226 lines
14 KiB
C
226 lines
14 KiB
C
/*******************************************************************************
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* Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
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* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Except as contained in this notice, the name of Maxim Integrated
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* Products, Inc. shall not be used except as stated in the Maxim Integrated
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* Products, Inc. Branding Policy.
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*
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* The mere transfer of this software does not imply any licenses
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* of trade secrets, proprietary technology, copyrights, patents,
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* trademarks, maskwork rights, or any other form of intellectual
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* property whatsoever. Maxim Integrated Products, Inc. retains all
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* ownership rights.
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*******************************************************************************
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*/
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#ifndef _MXC_SPI_REGS_H
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#define _MXC_SPI_REGS_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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/**
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* @file spi_regs.h
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* @addtogroup spi SPI
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* @{
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*/
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/* Offset Register Description
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====== ============================================ */
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typedef struct {
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__IO uint32_t mstr_cfg; /* 0x0000 SPI Master Configuration Register */
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__IO uint32_t ss_sr_polarity; /* 0x0004 Polarity Control for SS and SR Signals */
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__IO uint32_t gen_ctrl; /* 0x0008 SPI Master General Control Register */
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__IO uint32_t fifo_ctrl; /* 0x000C SPI Master FIFO Control Register */
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__IO uint32_t spcl_ctrl; /* 0x0010 SPI Master Special Mode Controls */
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__IO uint32_t intfl; /* 0x0014 SPI Master Interrupt Flags */
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__IO uint32_t inten; /* 0x0018 SPI Master Interrupt Enable/Disable Settings */
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__I uint32_t rsv001C; /* 0x001C Deprecated - was SPI_AHB_RETRY */
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} mxc_spi_regs_t;
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/**
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* @brief TX FIFO register. Can do 8, 16, or 32 bit access.
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*/
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typedef struct {
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union {
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__O uint8_t txfifo_8;
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__O uint16_t txfifo_16;
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__O uint32_t txfifo_32;
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};
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} mxc_spi_txfifo_regs_t;
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/**
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* @brief RX FIFO register. Can do 8, 16, or 32 bit access.
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*/
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typedef struct {
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union {
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__I uint8_t rxfifo_8;
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__I uint16_t rxfifo_16;
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__I uint32_t rxfifo_32;
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};
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} mxc_spi_rxfifo_regs_t;
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/*
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Register offsets for module SPI.
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*/
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#define MXC_R_SPI_OFFS_MSTR_CFG ((uint32_t)0x00000000UL)
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#define MXC_R_SPI_OFFS_SS_SR_POLARITY ((uint32_t)0x00000004UL)
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#define MXC_R_SPI_OFFS_GEN_CTRL ((uint32_t)0x00000008UL)
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#define MXC_R_SPI_OFFS_FIFO_CTRL ((uint32_t)0x0000000CUL)
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#define MXC_R_SPI_OFFS_SPCL_CTRL ((uint32_t)0x00000010UL)
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#define MXC_R_SPI_OFFS_INTFL ((uint32_t)0x00000014UL)
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#define MXC_R_SPI_OFFS_INTEN ((uint32_t)0x00000018UL)
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#define MXC_R_SPI_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL)
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#define MXC_R_SPI_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL)
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/*
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Field positions and masks for module SPI.
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*/
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#define MXC_F_SPI_MSTR_CFG_SLAVE_SEL_POS 0
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#define MXC_F_SPI_MSTR_CFG_SLAVE_SEL ((uint32_t)(0x00000007UL << MXC_F_SPI_MSTR_CFG_SLAVE_SEL_POS))
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#define MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE_POS 3
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#define MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE_POS))
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#define MXC_F_SPI_MSTR_CFG_SPI_MODE_POS 4
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#define MXC_F_SPI_MSTR_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_SPI_MODE_POS))
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#define MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS 6
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#define MXC_F_SPI_MSTR_CFG_PAGE_SIZE ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS))
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#define MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS 8
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#define MXC_F_SPI_MSTR_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS))
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#define MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS 12
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#define MXC_F_SPI_MSTR_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS))
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#define MXC_F_SPI_MSTR_CFG_ACT_DELAY_POS 16
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#define MXC_F_SPI_MSTR_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_ACT_DELAY_POS))
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#define MXC_F_SPI_MSTR_CFG_INACT_DELAY_POS 18
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#define MXC_F_SPI_MSTR_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_INACT_DELAY_POS))
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#define MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK_POS 20
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#define MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK_POS))
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#define MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK_POS 24
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#define MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK_POS))
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#define MXC_V_SPI_MSTR_CFG_PAGE_SIZE_4B ((uint32_t)0x00000000UL)
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#define MXC_V_SPI_MSTR_CFG_PAGE_SIZE_8B ((uint32_t)0x00000001UL)
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#define MXC_V_SPI_MSTR_CFG_PAGE_SIZE_16B ((uint32_t)0x00000002UL)
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#define MXC_V_SPI_MSTR_CFG_PAGE_SIZE_32B ((uint32_t)0x00000003UL)
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#define MXC_S_SPI_MSTR_CFG_PAGE_4B (MXC_V_SPI_MSTR_CFG_PAGE_SIZE_4B << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS)
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#define MXC_S_SPI_MSTR_CFG_PAGE_8B (MXC_V_SPI_MSTR_CFG_PAGE_SIZE_8B << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS)
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#define MXC_S_SPI_MSTR_CFG_PAGE_16B (MXC_V_SPI_MSTR_CFG_PAGE_SIZE_16B << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS)
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#define MXC_S_SPI_MSTR_CFG_PAGE_32B (MXC_V_SPI_MSTR_CFG_PAGE_SIZE_32B << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS)
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#define MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY_POS 0
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#define MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY_POS))
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#define MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY_POS 8
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#define MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY_POS))
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#define MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN_POS 0
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#define MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN_POS))
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#define MXC_F_SPI_GEN_CTRL_TX_FIFO_EN_POS 1
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#define MXC_F_SPI_GEN_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_TX_FIFO_EN_POS))
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#define MXC_F_SPI_GEN_CTRL_RX_FIFO_EN_POS 2
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#define MXC_F_SPI_GEN_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_RX_FIFO_EN_POS))
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#define MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE_POS 3
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#define MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE_POS))
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#define MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT_POS 4
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#define MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT_POS))
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#define MXC_F_SPI_GEN_CTRL_BB_SR_IN_POS 5
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#define MXC_F_SPI_GEN_CTRL_BB_SR_IN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SR_IN_POS))
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#define MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT_POS 6
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#define MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT_POS))
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#define MXC_F_SPI_GEN_CTRL_BB_SDIO_IN_POS 8
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#define MXC_F_SPI_GEN_CTRL_BB_SDIO_IN ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_IN_POS))
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#define MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT_POS 12
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#define MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT_POS))
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#define MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN_POS 16
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#define MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN_POS))
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#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL_POS 0
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#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL ((uint32_t)(0x0000000FUL << MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL_POS))
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#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS 8
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#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED ((uint32_t)(0x0000001FUL << MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS))
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#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS 16
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#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS))
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#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS 24
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#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS))
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#define MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE_POS 0
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#define MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE_POS))
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#define MXC_F_SPI_SPCL_CTRL_MISO_FC_EN_POS 1
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#define MXC_F_SPI_SPCL_CTRL_MISO_FC_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_SPCL_CTRL_MISO_FC_EN_POS))
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#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT_POS 4
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#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT_POS))
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#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS 8
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#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS))
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#define MXC_F_SPI_INTFL_TX_STALLED_POS 0
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#define MXC_F_SPI_INTFL_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_STALLED_POS))
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#define MXC_F_SPI_INTFL_RX_STALLED_POS 1
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#define MXC_F_SPI_INTFL_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_STALLED_POS))
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#define MXC_F_SPI_INTFL_TX_READY_POS 2
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#define MXC_F_SPI_INTFL_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_READY_POS))
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#define MXC_F_SPI_INTFL_RX_DONE_POS 3
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#define MXC_F_SPI_INTFL_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_DONE_POS))
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#define MXC_F_SPI_INTFL_TX_FIFO_AE_POS 4
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#define MXC_F_SPI_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_FIFO_AE_POS))
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#define MXC_F_SPI_INTFL_RX_FIFO_AF_POS 5
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#define MXC_F_SPI_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_FIFO_AF_POS))
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#define MXC_F_SPI_INTEN_TX_STALLED_POS 0
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#define MXC_F_SPI_INTEN_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_STALLED_POS))
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#define MXC_F_SPI_INTEN_RX_STALLED_POS 1
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#define MXC_F_SPI_INTEN_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_STALLED_POS))
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#define MXC_F_SPI_INTEN_TX_READY_POS 2
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#define MXC_F_SPI_INTEN_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_READY_POS))
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#define MXC_F_SPI_INTEN_RX_DONE_POS 3
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#define MXC_F_SPI_INTEN_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_DONE_POS))
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#define MXC_F_SPI_INTEN_TX_FIFO_AE_POS 4
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#define MXC_F_SPI_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_FIFO_AE_POS))
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#define MXC_F_SPI_INTEN_RX_FIFO_AF_POS 5
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#define MXC_F_SPI_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_FIFO_AF_POS))
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#define MXC_F_SPI_FIFO_DIR_POS 0
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#define MXC_F_SPI_FIFO_DIR ((uint32_t)(0x00000003UL << MXC_F_SPI_FIFO_DIR_POS))
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#define MXC_F_SPI_FIFO_UNIT_POS 2
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#define MXC_F_SPI_FIFO_UNIT ((uint32_t)(0x00000003UL << MXC_F_SPI_FIFO_UNIT_POS))
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#define MXC_F_SPI_FIFO_SIZE_POS 4
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#define MXC_F_SPI_FIFO_SIZE ((uint32_t)(0x0000000FUL << MXC_F_SPI_FIFO_SIZE_POS))
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#define MXC_F_SPI_FIFO_WIDTH_POS 9
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#define MXC_F_SPI_FIFO_WIDTH ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_WIDTH_POS))
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#define MXC_F_SPI_FIFO_ALT_POS 11
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#define MXC_F_SPI_FIFO_ALT ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_ALT_POS))
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#define MXC_F_SPI_FIFO_FLOW_POS 12
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#define MXC_F_SPI_FIFO_FLOW ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_FLOW_POS))
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#define MXC_F_SPI_FIFO_DASS_POS 13
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#define MXC_F_SPI_FIFO_DASS ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_DASS_POS))
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#ifdef __cplusplus
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}
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#endif
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/**
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* @}
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*/
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#endif /* _MXC_SPI_REGS_H */
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