mirror of https://github.com/ARMmbed/mbed-os.git
319 lines
10 KiB
C
319 lines
10 KiB
C
/**
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******************************************************************************
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* @file stm32l1xx_ll_rcc.c
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* @author MCD Application Team
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* @brief RCC LL module driver.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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#if defined(USE_FULL_LL_DRIVER)
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/* Includes ------------------------------------------------------------------*/
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#include "stm32l1xx_ll_rcc.h"
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/** @addtogroup STM32L1xx_LL_Driver
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* @{
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*/
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#if defined(RCC)
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/** @defgroup RCC_LL RCC
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/* Private macros ------------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/** @defgroup RCC_LL_Private_Functions RCC Private functions
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* @{
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*/
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uint32_t RCC_GetSystemClockFreq(void);
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uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
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uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
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uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
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uint32_t RCC_PLL_GetFreqDomain_SYS(void);
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @addtogroup RCC_LL_Exported_Functions
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* @{
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*/
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/** @addtogroup RCC_LL_EF_Init
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* @{
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*/
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/**
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* @brief Reset the RCC clock configuration to the default reset state.
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* @note The default reset state of the clock configuration is given below:
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* - MSI ON and used as system clock source
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* - HSE, HSI and PLL OFF
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* - AHB, APB1 and APB2 prescaler set to 1.
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* - CSS, MCO OFF
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* - All interrupts disabled
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* @note This function doesn't modify the configuration of the
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* - Peripheral clocks
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* - LSI, LSE and RTC clocks
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* @retval An ErrorStatus enumeration value:
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* - SUCCESS: RCC registers are de-initialized
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* - ERROR: not applicable
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*/
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ErrorStatus LL_RCC_DeInit(void)
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{
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uint32_t vl_mask = 0U;
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/* Set MSION bit */
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LL_RCC_MSI_Enable();
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/* Insure MSIRDY bit is set before writing default MSIRANGE value */
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while (LL_RCC_MSI_IsReady() == 0U)
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{
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__NOP();
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}
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/* Set MSIRANGE default value */
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LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_5);
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/* Set MSITRIM bits to the reset value*/
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LL_RCC_MSI_SetCalibTrimming(0U);
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/* Set HSITRIM bits to the reset value*/
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LL_RCC_HSI_SetCalibTrimming(0x10U);
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/* Reset SW, HPRE, PPRE and MCOSEL bits */
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vl_mask = 0xFFFFFFFFU;
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CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCOSEL));
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LL_RCC_WriteReg(CFGR, vl_mask);
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/* Reset HSION, HSEON, CSSON, PLLON bits */
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vl_mask = 0xFFFFFFFFU;
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CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_HSION));
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LL_RCC_WriteReg(CR, vl_mask);
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/* Reset HSEBYP bit */
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LL_RCC_HSE_DisableBypass();
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/* Reset CFGR register */
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LL_RCC_WriteReg(CFGR, 0x00000000U);
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/* Clear pending flags */
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#if defined(RCC_LSECSS_SUPPORT)
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vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_MSIRDYC | LL_RCC_CIR_LSECSSC | LL_RCC_CIR_CSSC);
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#else
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vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_MSIRDYC | LL_RCC_CIR_CSSC);
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#endif /* RCC_LSECSS_SUPPORT */
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SET_BIT(RCC->CIR, vl_mask);
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/* Disable all interrupts */
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LL_RCC_WriteReg(CIR, 0x00000000U);
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return SUCCESS;
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}
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/**
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* @}
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*/
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/** @addtogroup RCC_LL_EF_Get_Freq
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* @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
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* and different peripheral clocks available on the device.
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* @note If SYSCLK source is MSI, function returns values based on MSI clock(*)
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* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
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* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
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* @note If SYSCLK source is PLL, function returns values based on
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* HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
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* @note (*) MSI clock depends on the selected MSI range but the real value
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* may vary depending on the variations in voltage and temperature.
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* @note (**) HSI_VALUE is a defined constant but the real value may vary
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* depending on the variations in voltage and temperature.
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* @note (***) HSE_VALUE is a defined constant, user has to ensure that
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* HSE_VALUE is same as the real frequency of the crystal used.
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* Otherwise, this function may have wrong result.
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* @note The result of this function could be incorrect when using fractional
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* value for HSE crystal.
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* @note This function can be used by the user application to compute the
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* baud-rate for the communication peripherals or configure other parameters.
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* @{
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*/
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/**
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* @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
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* @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
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* must be called to update structure fields. Otherwise, any
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* configuration based on this function will be incorrect.
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* @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
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* @retval None
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*/
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void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
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{
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/* Get SYSCLK frequency */
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RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
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/* HCLK clock frequency */
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RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
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/* PCLK1 clock frequency */
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RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
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/* PCLK2 clock frequency */
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RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/** @addtogroup RCC_LL_Private_Functions
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* @{
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*/
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/**
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* @brief Return SYSTEM clock frequency
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* @retval SYSTEM clock frequency (in Hz)
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*/
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uint32_t RCC_GetSystemClockFreq(void)
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{
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uint32_t frequency = 0U;
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/* Get SYSCLK source -------------------------------------------------------*/
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switch (LL_RCC_GetSysClkSource())
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{
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case LL_RCC_SYS_CLKSOURCE_STATUS_MSI: /* MSI used as system clock source */
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frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
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break;
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case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
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frequency = HSI_VALUE;
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break;
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case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
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frequency = HSE_VALUE;
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break;
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case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
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frequency = RCC_PLL_GetFreqDomain_SYS();
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break;
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default:
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frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
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break;
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}
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return frequency;
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}
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/**
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* @brief Return HCLK clock frequency
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* @param SYSCLK_Frequency SYSCLK clock frequency
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* @retval HCLK clock frequency (in Hz)
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*/
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uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
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{
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/* HCLK clock frequency */
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return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
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}
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/**
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* @brief Return PCLK1 clock frequency
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* @param HCLK_Frequency HCLK clock frequency
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* @retval PCLK1 clock frequency (in Hz)
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*/
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uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
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{
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/* PCLK1 clock frequency */
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return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
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}
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/**
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* @brief Return PCLK2 clock frequency
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* @param HCLK_Frequency HCLK clock frequency
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* @retval PCLK2 clock frequency (in Hz)
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*/
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uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
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{
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/* PCLK2 clock frequency */
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return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
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}
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/**
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* @brief Return PLL clock frequency used for system domain
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* @retval PLL clock frequency (in Hz)
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*/
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uint32_t RCC_PLL_GetFreqDomain_SYS(void)
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{
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uint32_t pllinputfreq = 0U, pllsource = 0U;
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/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */
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/* Get PLL source */
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pllsource = LL_RCC_PLL_GetMainSource();
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switch (pllsource)
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{
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case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
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pllinputfreq = HSI_VALUE;
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break;
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case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
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pllinputfreq = HSE_VALUE;
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break;
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default:
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pllinputfreq = HSI_VALUE;
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break;
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}
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return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetDivider());
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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#endif /* defined(RCC) */
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/**
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* @}
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*/
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#endif /* USE_FULL_LL_DRIVER */
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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