mirror of https://github.com/ARMmbed/mbed-os.git
598 lines
22 KiB
C
598 lines
22 KiB
C
/**
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******************************************************************************
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* @file stm32h7xx_hal_pwr.h
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* @author MCD Application Team
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* @brief Header file of PWR HAL module.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef STM32H7xx_HAL_PWR_H
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#define STM32H7xx_HAL_PWR_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32h7xx_hal_def.h"
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/** @addtogroup STM32H7xx_HAL_Driver
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* @{
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*/
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/** @addtogroup PWR
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup PWR_Exported_Types PWR Exported Types
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* @{
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*/
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/**
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* @brief PWR PVD configuration structure definition
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*/
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typedef struct
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{
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uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
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This parameter can be a value of @ref PWR_PVD_detection_level */
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uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
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This parameter can be a value of @ref PWR_PVD_Mode */
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}PWR_PVDTypeDef;
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup PWR_Exported_Constants PWR Exported Constants
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* @{
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*/
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/** @defgroup PWR_PVD_detection_level PWR PVD detection level
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* @{
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*/
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#define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 /*!< Programmable voltage detector level 0 selection : 1V95 */
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#define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 /*!< Programmable voltage detector level 1 selection : 2V1 */
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#define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 /*!< Programmable voltage detector level 2 selection : 2V25 */
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#define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 /*!< Programmable voltage detector level 3 selection : 2V4 */
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#define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 /*!< Programmable voltage detector level 4 selection : 2V55 */
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#define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 /*!< Programmable voltage detector level 5 selection : 2V7 */
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#define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 /*!< Programmable voltage detector level 6 selection : 2V85 */
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#define PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7 /*!< External input analog voltage (Compare internally to VREFINT) */
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/**
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* @}
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*/
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/** @defgroup PWR_PVD_Mode PWR PVD Mode
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* @{
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*/
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#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Basic mode is used */
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#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */
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#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */
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#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
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#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */
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#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */
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#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */
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/**
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* @}
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*/
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/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
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* @{
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*/
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#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U)
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#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS
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/**
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* @}
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*/
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/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
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* @{
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*/
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#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U)
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#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U)
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/**
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* @}
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*/
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/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
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* @{
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*/
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#define PWR_STOPENTRY_WFI ((uint8_t)0x01U)
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#define PWR_STOPENTRY_WFE ((uint8_t)0x02U)
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/**
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* @}
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*/
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/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
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* @{
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*/
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#define PWR_REGULATOR_VOLTAGE_SCALE0 ((uint32_t)0x00000000)
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#define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0)
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#define PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_D3CR_VOS_1)
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#define PWR_REGULATOR_VOLTAGE_SCALE3 (PWR_D3CR_VOS_0)
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/**
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* @}
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*/
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/** @defgroup PWR_Flag PWR Flag
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* @{
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*/
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#define PWR_FLAG_STOP ((uint8_t)0x01U)
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#define PWR_FLAG_SB_D1 ((uint8_t)0x02U)
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#define PWR_FLAG_SB_D2 ((uint8_t)0x03U)
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#define PWR_FLAG_SB ((uint8_t)0x04U)
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#if defined(DUAL_CORE)
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#define PWR_FLAG_CPU_HOLD ((uint8_t)0x05U)
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#define PWR_FLAG_CPU2_HOLD ((uint8_t)0x06U)
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#define PWR_FLAG2_STOP ((uint8_t)0x07U)
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#define PWR_FLAG2_SB_D1 ((uint8_t)0x08U)
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#define PWR_FLAG2_SB_D2 ((uint8_t)0x09U)
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#define PWR_FLAG2_SB ((uint8_t)0x0AU)
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#endif /*DUAL_CORE*/
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#define PWR_FLAG_PVDO ((uint8_t)0x0BU)
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#define PWR_FLAG_AVDO ((uint8_t)0x0CU)
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#define PWR_FLAG_ACTVOSRDY ((uint8_t)0x0DU)
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#define PWR_FLAG_ACTVOS ((uint8_t)0x0EU)
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#define PWR_FLAG_BRR ((uint8_t)0x0FU)
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#define PWR_FLAG_VOSRDY ((uint8_t)0x10U)
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#if defined(SMPS)
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#define PWR_FLAG_SMPSEXTRDY ((uint8_t)0x11U)
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#else
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#define PWR_FLAG_SCUEN ((uint8_t)0x11U)
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#endif /* SMPS */
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/**
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* @}
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*/
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/** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask
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* @{
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*/
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#define PWR_EWUP_MASK ((uint32_t)0x0FFF3F3FU)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/** @defgroup PWR_Exported_Macro PWR Exported Macro
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* @{
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*/
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/** @brief macros configure the main internal regulator output voltage.
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* @param __REGULATOR__: specifies the regulator output voltage to achieve
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* a tradeoff between performance and power consumption when the device does
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* not operate at the maximum frequency (refer to the datasheets for more details).
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* This parameter can be one of the following values:
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* @arg PWR_REGULATOR_VOLTAGE_SCALE0: Regulator voltage output Scale 0 mode
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* @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
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* @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
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* @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
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* @note PWR_REGULATOR_VOLTAGE_SCALE0 is only possible when Vcore is supplied from LDO.
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* the SYSCFG Clock must be enabled before selecting PWR_REGULATOR_VOLTAGE_SCALE0
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* using macro __HAL_RCC_SYSCFG_CLK_ENABLE().
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* Transition to PWR_REGULATOR_VOLTAGE_SCALE0 is only possible when the system is already in
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* PWR_REGULATOR_VOLTAGE_SCALE1.
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* transition from PWR_REGULATOR_VOLTAGE_SCALE0 is only possible to PWR_REGULATOR_VOLTAGE_SCALE1
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* then once in PWR_REGULATOR_VOLTAGE_SCALE1 it is possible to switch to another voltage scale.
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* After each regulator voltage setting, wait on PWR_FLAG_VOSRDY to be set using macro __HAL_PWR_GET_FLAG
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* To enter low power mode , and if current regulator voltage is PWR_REGULATOR_VOLTAGE_SCALE0 then first
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* switch to PWR_REGULATOR_VOLTAGE_SCALE1 before entering low power mode.
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*
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* @retval None
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*/
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#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \
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do { \
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__IO uint32_t tmpreg = 0x00; \
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if((__REGULATOR__) == PWR_REGULATOR_VOLTAGE_SCALE0) \
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{ \
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MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); \
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/* Delay after setting the voltage scaling */ \
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tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \
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MODIFY_REG(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN, SYSCFG_PWRCR_ODEN); \
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/* Delay after setting the syscfg boost setting */ \
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tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \
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} \
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else \
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{ \
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CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \
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/* Delay after setting the syscfg boost setting */ \
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tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \
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MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \
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tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \
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} \
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UNUSED(tmpreg); \
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} while(0)
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#if defined(DUAL_CORE)
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/** @brief Check PWR PVD/AVD and VOSflags are set or not.
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* @param __FLAG__: specifies the flag to check.
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* This parameter can be one of the following values:
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* @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
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* by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode.
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* For this reason, this bit is equal to 0 after Standby or reset
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* until the PVDE bit is set.
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* @arg PWR_FLAG_AVDO: AVD Output. This flag is valid only if AVD is enabled
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* by the HAL_PWREx_EnableAVD() function. The AVD is stopped by Standby mode.
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* For this reason, this bit is equal to 0 after Standby or reset
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* until the AVDE bit is set.
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* @arg PWR_FLAG_ACTVOSRDY: This flag indicates that the Regulator voltage
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* scaling output selection is ready.
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* @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
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* scaling output selection is ready.
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* @arg PWR_FLAG_SMPSEXTRDY: SMPS External supply ready flag.
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* @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
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* when the device wakes up from Standby mode or by a system reset
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* or power reset.
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* @arg PWR_FLAG_SB: StandBy flag
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* @arg PWR_FLAG_STOP: STOP flag
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* @arg PWR_FLAG_SB_D1: StandBy D1 flag
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* @arg PWR_FLAG_SB_D2: StandBy D2 flag
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* @arg PWR_FLAG_CPU1_HOLD: CPU1 system wake up with hold
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* @arg PWR_FLAG_CPU2_HOLD: CPU2 system wake up with hold
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* @retval The new state of __FLAG__ (TRUE or FALSE).
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*/
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#define __HAL_PWR_GET_FLAG(__FLAG__) ( \
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((__FLAG__) == PWR_FLAG_PVDO)?((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) : \
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((__FLAG__) == PWR_FLAG_AVDO)?((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) : \
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((__FLAG__) == PWR_FLAG_ACTVOSRDY)?((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) : \
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((__FLAG__) == PWR_FLAG_VOSRDY)?((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) : \
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((__FLAG__) == PWR_FLAG_SMPSEXTRDY)?((PWR->CR3 & PWR_CR3_SMPSEXTRDY) == PWR_CR3_SMPSEXTRDY) : \
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((__FLAG__) == PWR_FLAG_BRR)?((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) : \
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((__FLAG__) == PWR_FLAG_CPU_HOLD)?((PWR->CPU2CR & PWR_CPU2CR_HOLD1F) == PWR_CPU2CR_HOLD1F) : \
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((__FLAG__) == PWR_FLAG_CPU2_HOLD)?((PWR->CPUCR & PWR_CPUCR_HOLD2F) == PWR_CPUCR_HOLD2F) : \
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((__FLAG__) == PWR_FLAG_SB)?(READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF) == PWR_CPUCR_SBF) : \
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((__FLAG__) == PWR_FLAG2_SB)?(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF) == PWR_CPU2CR_SBF) : \
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((__FLAG__) == PWR_FLAG_STOP)?(READ_BIT(PWR->CPUCR, PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) : \
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((__FLAG__) == PWR_FLAG2_STOP)?(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_STOPF) == PWR_CPU2CR_STOPF) : \
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((__FLAG__) == PWR_FLAG_SB_D1)?(READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) : \
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((__FLAG__) == PWR_FLAG2_SB_D1)?(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D1) == PWR_CPU2CR_SBF_D1) : \
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((__FLAG__) == PWR_FLAG_SB_D2)?(READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) : \
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(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D2) == PWR_CPU2CR_SBF_D2))
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#else
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/** @brief Check PWR PVD/AVD and VOSflags are set or not.
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* @param __FLAG__: specifies the flag to check.
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* This parameter can be one of the following values:
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* @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
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* by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode.
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* For this reason, this bit is equal to 0 after Standby or reset
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* until the PVDE bit is set.
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* @arg PWR_FLAG_AVDO: AVD Output. This flag is valid only if AVD is enabled
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* by the HAL_PWREx_EnableAVD() function. The AVD is stopped by Standby mode.
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* For this reason, this bit is equal to 0 after Standby or reset
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* until the AVDE bit is set.
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* @arg PWR_FLAG_ACTVOSRDY: This flag indicates that the Regulator voltage
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* scaling output selection is ready.
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* @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
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* scaling output selection is ready.
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* @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
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* when the device wakes up from Standby mode or by a system reset
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* or power reset.
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* @arg PWR_FLAG_SB: StandBy flag
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* @arg PWR_FLAG_STOP: STOP flag
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* @arg PWR_FLAG_SB_D1: StandBy D1 flag
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* @arg PWR_FLAG_SB_D2: StandBy D2 flag
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* @retval The new state of __FLAG__ (TRUE or FALSE).
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*/
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#define __HAL_PWR_GET_FLAG(__FLAG__) ( \
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((__FLAG__) == PWR_FLAG_PVDO)?((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) : \
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((__FLAG__) == PWR_FLAG_AVDO)?((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) : \
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((__FLAG__) == PWR_FLAG_ACTVOSRDY)?((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) : \
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((__FLAG__) == PWR_FLAG_VOSRDY)?((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) : \
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((__FLAG__) == PWR_FLAG_SCUEN)?((PWR->CR3 & PWR_CR3_SCUEN) == PWR_CR3_SCUEN) : \
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((__FLAG__) == PWR_FLAG_BRR)?((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) : \
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((__FLAG__) == PWR_FLAG_SB)?((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) : \
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((__FLAG__) == PWR_FLAG_STOP)?((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) : \
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((__FLAG__) == PWR_FLAG_SB_D1)?((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) : \
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((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2))
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#endif /*DUAL_CORE*/
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#if defined(DUAL_CORE)
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/** @brief Clear PWR flags.
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* @param __FLAG__: specifies the flag to clear.
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* This parameter can be one of the following values:
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* @arg PWR_FLAG_SB: Standby flag.
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* @arg PWR_CPU_FLAGS: Clear HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2 CPU flags.
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* @retval None.
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*/
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#define __HAL_PWR_CLEAR_FLAG(__FLAG__) \
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do { \
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SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF); \
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SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF); \
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} while(0)
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#else
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/** @brief Clear PWR flags.
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* @param __FLAG__: specifies the flag to clear.
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* This parameter can be one of the following values:
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* @arg PWR_FLAG_SB: Standby flag.
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* @arg PWR_CPU_FLAGS: Clear STOPF, SBF, SBF_D1, and SBF_D2 CPU flags.
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* @retval None.
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*/
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#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)
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#endif /*DUAL_CORE*/
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/**
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* @brief Enable the PVD EXTI Line 16.
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* @retval None.
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*/
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#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
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#if defined(DUAL_CORE)
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/**
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* @brief Enable the PVD EXTI D2 Line 16.
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* @retval None.
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*/
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#define __HAL_PWR_PVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
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#endif /*DUAL_CORE*/
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/**
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* @brief Disable the PVD EXTI Line 16.
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* @retval None.
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*/
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#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
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#if defined(DUAL_CORE)
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/**
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* @brief Disable the PVD EXTI D2 Line 16.
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* @retval None.
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*/
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#define __HAL_PWR_PVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
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#endif /*DUAL_CORE*/
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/**
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* @brief Enable event on PVD EXTI Line 16.
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* @retval None.
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*/
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#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
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#if defined(DUAL_CORE)
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/**
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* @brief Enable event on PVD EXTI D2 Line.
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* @retval None.
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*/
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#define __HAL_PWR_PVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
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#endif /*DUAL_CORE*/
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/**
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* @brief Disable event on PVD EXTI Line 16.
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* @retval None.
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*/
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#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
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#if defined(DUAL_CORE)
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/**
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* @brief Disable event on PVD EXTI D2 Line.
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* @retval None.
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*/
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#define __HAL_PWR_PVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
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#endif /*DUAL_CORE*/
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/**
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* @brief Enable the PVD Extended Interrupt Rising Trigger.
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* @retval None.
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*/
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#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
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/**
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* @brief Disable the PVD Extended Interrupt Rising Trigger.
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* @retval None.
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*/
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#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
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/**
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* @brief Enable the PVD Extended Interrupt Falling Trigger.
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* @retval None.
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*/
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#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
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/**
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* @brief Disable the PVD Extended Interrupt Falling Trigger.
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* @retval None.
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*/
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#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
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/**
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* @brief PVD EXTI line configuration: set rising & falling edge trigger.
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* @retval None.
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*/
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#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
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do { \
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__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \
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__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \
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} while(0);
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/**
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* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
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* @retval None.
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*/
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#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
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do { \
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__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
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__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
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} while(0);
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/**
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* @brief Check whether the specified PVD EXTI interrupt flag is set or not.
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* @retval EXTI PVD Line Status.
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*/
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#define __HAL_PWR_PVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? SET : RESET)
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#if defined(DUAL_CORE)
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/**
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* @brief checks whether the specified PVD Exti interrupt flag is set or not.
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* @retval EXTI D2 PVD Line Status.
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*/
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#define __HAL_PWR_PVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? SET : RESET)
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#endif /*DUAL_CORE*/
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/**
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* @brief Clear the PVD EXTI flag.
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* @retval None.
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*/
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#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD)
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#if defined(DUAL_CORE)
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/**
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* @brief Clear the PVD EXTI D2 flag.
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* @retval None.
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*/
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#define __HAL_PWR_PVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD)
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#endif /*DUAL_CORE*/
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/**
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* @brief Generates a Software interrupt on PVD EXTI line.
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* @retval None.
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*/
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#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
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/**
|
|
* @}
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|
*/
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/* Include PWR HAL Extension module */
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#include "stm32h7xx_hal_pwr_ex.h"
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/* Exported functions --------------------------------------------------------*/
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/** @addtogroup PWR_Exported_Functions PWR Exported Functions
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* @{
|
|
*/
|
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/** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization functions
|
|
* @{
|
|
*/
|
|
/* Initialization and de-initialization functions *****************************/
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|
void HAL_PWR_DeInit(void);
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void HAL_PWR_EnableBkUpAccess(void);
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|
void HAL_PWR_DisableBkUpAccess(void);
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|
/**
|
|
* @}
|
|
*/
|
|
|
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/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
|
|
* @{
|
|
*/
|
|
/* Peripheral Control functions **********************************************/
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/* PVD configuration */
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|
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
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void HAL_PWR_EnablePVD(void);
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|
void HAL_PWR_DisablePVD(void);
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|
|
/* WakeUp pins configuration */
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|
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
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|
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
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|
|
/* Low Power modes entry */
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|
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
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|
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
|
|
void HAL_PWR_EnterSTANDBYMode(void);
|
|
|
|
/* Power PVD IRQ Handler */
|
|
void HAL_PWR_PVD_IRQHandler(void);
|
|
void HAL_PWR_PVDCallback(void);
|
|
|
|
/* Cortex System Control functions *******************************************/
|
|
void HAL_PWR_EnableSleepOnExit(void);
|
|
void HAL_PWR_DisableSleepOnExit(void);
|
|
void HAL_PWR_EnableSEVOnPend(void);
|
|
void HAL_PWR_DisableSEVOnPend(void);
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Private types -------------------------------------------------------------*/
|
|
/* Private variables ---------------------------------------------------------*/
|
|
/* Private constants ---------------------------------------------------------*/
|
|
/** @defgroup PWR_Private_Constants PWR Private Constants
|
|
* @{
|
|
*/
|
|
|
|
/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
|
|
* @{
|
|
*/
|
|
/*!< External interrupt line 16 Connected to the PVD EXTI Line */
|
|
#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR1_IM16)
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
/* Private macros ------------------------------------------------------------*/
|
|
/** @defgroup PWR_Private_Macros PWR Private Macros
|
|
* @{
|
|
*/
|
|
|
|
/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
|
|
* @{
|
|
*/
|
|
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
|
|
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
|
|
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
|
|
((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
|
|
|
|
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
|
|
((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
|
|
((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
|
|
((MODE) == PWR_PVD_MODE_NORMAL))
|
|
|
|
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
|
|
((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
|
|
|
|
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
|
|
|
|
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
|
|
#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
|
|
((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
|
|
((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
|
|
#endif /* STM32H7xx_HAL_PWR_H */
|
|
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|