mirror of https://github.com/ARMmbed/mbed-os.git
116 lines
2.9 KiB
C
116 lines
2.9 KiB
C
/* mbed Microcontroller Library
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* Copyright (c) 2019 ARM Limited
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/* Low-level implementation of the us ticker for MSP432. The Timer32
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* modules can not be used for this purpose, because they do not
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* generate irqs in free-running mode. So the only remaing choice
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* are the Timer A modules, which are only 16 bit, but support irqs
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* when operated in continuous mode. Timer A3 is choosen here, which
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* could be made configurable in the future.
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*
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* See hal/us_ticker_api.h for a detailed description of the following
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* functions.
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*/
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#if DEVICE_USTICKER
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#include <stdint.h>
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#include "us_ticker_api.h"
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#include "mbed_assert.h"
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extern void us_ticker_irq_handler(void);
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void us_ticker_init(void)
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{
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// Calculate the Timer A divisors (shift and remainder)
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uint32_t prescale = SubsystemMasterClock / 1000000;
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int shifts = 0;
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for (shifts = 0; shifts < 3; shifts++) {
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if (prescale & 0x1) {
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break;
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} else {
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prescale >>= 1;
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}
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}
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// Check that we have at least a 1MHz clock
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MBED_ASSERT(prescale && (prescale < 9));
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// initialize the registers and set prescalers
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TIMER_A3->CTL = (shifts << TIMER_A_CTL_ID_OFS) |
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TIMER_A_CTL_SSEL__SMCLK |
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TIMER_A_CTL_MC__CONTINUOUS;
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TIMER_A3->CCTL[0] = 0;
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TIMER_A3->EX0 = prescale - 1;
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// enable IRQ in NVIC
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NVIC_EnableIRQ(TA3_0_IRQn);
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}
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void us_ticker_free(void)
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{
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// Reset the ctrl registers to default value
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TIMER_A3->CTL = 0;
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TIMER_A3->CCTL[0] = 0;
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// Disable timer interrupt
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NVIC_DisableIRQ(TA3_0_IRQn);
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}
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uint32_t us_ticker_read(void)
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{
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return TIMER_A3->R;
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}
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void us_ticker_set_interrupt(timestamp_t timestamp)
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{
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TIMER_A3->CCR [0] = timestamp;
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TIMER_A3->CCTL[0] = TIMER_A_CCTLN_CCIE;
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}
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void us_ticker_disable_interrupt(void)
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{
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TIMER_A3->CCTL[0] &= ~TIMER_A_CCTLN_CCIE;
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}
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void us_ticker_clear_interrupt(void)
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{
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TIMER_A3->CCTL[0] &= ~TIMER_A_CCTLN_CCIFG;
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}
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void us_ticker_fire_interrupt(void)
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{
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NVIC_SetPendingIRQ(TA3_0_IRQn);
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}
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const ticker_info_t *us_ticker_get_info(void)
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{
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static const ticker_info_t info = {
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1000000, // 1 MHz
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16 // 16 bit counter
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};
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return &info;
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}
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/* Timer_A3 interrupt handler */
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void TA3_0_IRQHandler()
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{
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us_ticker_irq_handler();
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}
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#endif /* DEVICE_USTICKER */
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