mirror of https://github.com/ARMmbed/mbed-os.git
358 lines
9.9 KiB
C
Executable File
358 lines
9.9 KiB
C
Executable File
/****************************************************************************
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*
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* Copyright 2020 Samsung Electronics All Rights Reserved.
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing,
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* software distributed under the License is distributed on an
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* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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* either express or implied. See the License for the specific
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* language governing permissions and limitations under the License.
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*
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****************************************************************************/
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#include "gpio_api.h"
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#include "pinmap.h"
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#include "gpio.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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// BIT MASK
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#define MASK_1_BIT (0x00000001)
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#define MASK_2_BIT (0x00000003)
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#define MASK_3_BIT (0x00000007)
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#define MASK_4_BIT (0x0000000F)
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#define MASK_5_BIT (0x0000001F)
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#define MASK_6_BIT (0x0000003F)
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#define MASK_7_BIT (0x0000007F)
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#define SetBits(uAddr, uBaseBit, uMaskValue, uSetValue) \
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putreg32((getreg32(uAddr) & ~((uMaskValue)<<(uBaseBit))) | (((uMaskValue)&(uSetValue))<<(uBaseBit)), uAddr)
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#define GetBits(uAddr, uBaseBit, uMaskValue) \
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((getreg32(uAddr)>>(uBaseBit))&(uMaskValue))
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#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
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int gpio_pin_mode(PinName pin, PinMode mode);
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uint32_t get_tmux_addr(enum gpio_id_ id)
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{
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uint32_t i;
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uint32_t offset;
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const struct tmux_range_ tmux_range[] = {
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// addr start end
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{0x03C, 24, 72},
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{0x100, 0, 23},
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};
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offset = 0;
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for (i = 0; i < ARRAY_SIZE(tmux_range); i++) {
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if ((id >= tmux_range[i].start_num) && (id <= tmux_range[i].end_num)) {
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offset = tmux_range[i].addr + ((id - tmux_range[i].start_num) * 4);
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break;
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}
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}
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return (TOP_MUX_BASE + offset);
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}
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void gpio_set_input_enable(enum gpio_id_ id, enum in_enable_ inen)
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{
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uint32_t addr;
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addr = get_tmux_addr(id);
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SetBits(addr, BITPOS_OE, MASK_1_BIT, OUT_DIS);
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SetBits(addr, BITPOS_IE, MASK_1_BIT, inen);
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}
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void gpio_set_func(enum gpio_id_ id, enum nmux_func_ func)
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{
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uint32_t addr;
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addr = get_tmux_addr(id);
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SetBits(addr, BITPOS_FUNC, MASK_3_BIT, func);
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}
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void gpio_set_pupd(enum gpio_id_ id, enum pull_up_down_ pupd)
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{
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uint32_t addr;
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addr = get_tmux_addr(id);
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if (pupd == GPIO_PUPD_DIS) {
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SetBits(addr, BITPOS_PUPD + 1, MASK_1_BIT, pupd);
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} else {
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SetBits(addr, BITPOS_PUPD, MASK_2_BIT, pupd);
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}
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}
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void gpio_set_ds(enum gpio_id_ id, enum drive_strength_ ds)
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{
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uint32_t addr;
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addr = get_tmux_addr(id);
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SetBits(addr, BITPOS_DS, MASK_2_BIT, ds);
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}
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void s5js100_setdrv(uint32_t cfgset)
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{
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uint32_t ds;
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uint32_t pin;
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/* CAVEAT: GPIO_FAST|SLOWXXX is compatible with GPIO_DRV_XXX */
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ds = (cfgset & GPIO_DRVSTR_MASK) >> GPIO_DRVSTR_SHIFT;
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pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
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gpio_set_ds(pin, ds);
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}
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void s5js100_pullup(uint32_t cfgset)
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{
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uint32_t pin;
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uint32_t pupd;
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/* CAVEAT: GPIO_PUPD_XXX is compatible with GPIO_PUD_XXX */
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pupd = (cfgset & GPIO_PUPD_MASK) >> GPIO_PUPD_SHIFT;
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pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
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gpio_set_pupd(pin, pupd);
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}
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void s5js100_setintedge(unsigned int pin, int edge)
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{
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uint32_t group;
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uint32_t addr;
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uint32_t bitpos;
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group = pin >> 5; //group = 0, 1,
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addr = group << 2; // addr = 0x0, 0x4,
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bitpos = pin & 0x1F;
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switch (edge) {
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case LEVEL_LOW:
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putreg32(getreg32(GPIO_INT_METHOD_REG + addr) | (1 << bitpos), GPIO_INT_METHOD_REG + addr);
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putreg32(getreg32(GPIO_INT_POL_REG + addr) & ~(1 << bitpos), GPIO_INT_POL_REG + addr);
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break;
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case LEVEL_HIGH:
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putreg32(getreg32(GPIO_INT_METHOD_REG + addr) | (1 << bitpos), GPIO_INT_METHOD_REG + addr);
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putreg32(getreg32(GPIO_INT_POL_REG + addr) | (1 << bitpos), GPIO_INT_POL_REG + addr);
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break;
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case NEG_EDGE:
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putreg32(getreg32(GPIO_INT_METHOD_REG + addr) & ~(1 << bitpos), GPIO_INT_METHOD_REG + addr);
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putreg32(getreg32(GPIO_INT_BOTH_REG + addr) & ~(1 << bitpos), GPIO_INT_BOTH_REG + addr);
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putreg32(getreg32(GPIO_INT_POL_REG + addr) & ~(1 << bitpos), GPIO_INT_POL_REG + addr);
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//gpio_set_pupd(pin, GPIO_PULL_UP);
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break;
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case POS_EDGE:
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putreg32(getreg32(GPIO_INT_METHOD_REG + addr) & ~(1 << bitpos), GPIO_INT_METHOD_REG + addr);
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putreg32(getreg32(GPIO_INT_BOTH_REG + addr) & ~(1 << bitpos), GPIO_INT_BOTH_REG + addr);
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putreg32(getreg32(GPIO_INT_POL_REG + addr) | (1 << bitpos), GPIO_INT_POL_REG + addr);
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//gpio_set_pupd(pin, GPIO_PULL_DOWN);
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break;
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case BOTH_EDGE:
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putreg32(getreg32(GPIO_INT_METHOD_REG + addr) & ~(1 << bitpos), GPIO_INT_METHOD_REG + addr);
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putreg32(getreg32(GPIO_INT_BOTH_REG + addr) | (1 << bitpos), GPIO_INT_BOTH_REG + addr);
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break;
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default:
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break;
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}
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}
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void s5js100_setintmask(unsigned int pin, int mask)
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{
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uint32_t group;
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uint32_t addr;
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uint32_t bitpos;
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group = pin >> 5; //group = 0, 1,
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addr = group << 2; // addr = 0x0, 0x4,
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bitpos = pin & 0x1F;
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if (mask) {
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putreg32(getreg32(GPIO_INT_MASK_REG + addr) | (0 << bitpos), GPIO_INT_MASK_REG + addr); // int disable
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} else {
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putreg32(getreg32(GPIO_INT_MASK_REG + addr) | (1 << bitpos), GPIO_INT_MASK_REG + addr); // int enable
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}
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/* workaround, eint first is set pended if counter part has GPIO output */
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putreg32(getreg32(GPIO_INT_PEND_CLR_REG + addr) | (1 << bitpos), GPIO_INT_PEND_CLR_REG + addr); // pending clear
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}
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uint32_t s5js100_get_intpin(unsigned int ch)
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{
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uint32_t i;
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uint32_t pend = getreg32(GPIO_INT_PEND_CLR_REG + (ch * 0x4));
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for (i = 0; i < 32; i++) {
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if (pend & (0x1 << i)) {
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return i + ch * 32;
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}
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}
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return -1;
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}
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int s5js100_configinput(uint32_t cfgset)
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{
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uint32_t pin;
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uint32_t addr, bitpos;
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pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
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gpio_set_func(pin, GPIO_GPIO);
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/* Set as input */
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addr = GPIO_BASE + ((pin >> 5) << 2);
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bitpos = pin & 0x1F;
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putreg32(getreg32(addr) | (1 << bitpos), addr);
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gpio_set_input_enable(pin, IN_EN);
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/* Set pull-up/down */
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s5js100_pullup(cfgset);
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return 0;
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}
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int s5js100_configalt(uint32_t cfgset)
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{
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uint32_t pin;
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uint32_t func;
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pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
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func = (cfgset & GPIO_FUNC_MASK) >> GPIO_FUNC_SHIFT;
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gpio_set_func(pin, func);
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/* Set pull-up mode */
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s5js100_pullup(cfgset);
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/* Set drive strength */
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s5js100_setdrv(cfgset);
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return 0;
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}
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int s5js100_configinterrupt(uint32_t cfgset, uint32_t nirq)
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{
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uint32_t pin;
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pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
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if (cfgset & GPIO_EINT) {
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/*
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* First, configure the port as a generic input so that we have
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* a known starting point and consistent behavior during the
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* re-configuration.
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*/
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s5js100_configinput(cfgset);
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/* Then, just remember the rising/falling edge interrupt enabled */
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s5js100_setintedge(pin, (cfgset & GPIO_EINT_MASK) >> GPIO_EINT_SHIFT);
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s5js100_setintmask(pin, 0);
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/* workaround gpio eint clear int in NVIC side */
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///SetBits(0xE000E280, nirq - S5JS100_IRQ_FIRST, MASK_1_BIT, 0x1);
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} else {
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s5js100_setintmask(pin, 1);
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}
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return 0;
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}
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int s5js100_configgpio(uint32_t cfgset)
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{
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int ret = -1;
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ret = s5js100_configalt(cfgset);
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s5js100_configinterrupt(cfgset, (cfgset & GPIO_IRQ_MASK) >> GPIO_IRQ_SHIFT);
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return ret;
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}
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void s5js100_gpio_clear_pending(uint32_t pincfg)
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{
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uint32_t pin;
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uint32_t group;
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uint32_t addr;
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uint32_t bitpos;
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pin = (pincfg & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
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group = pin >> 5; //group = 0, 1,
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addr = group << 2; // addr = 0x0, 0x4,
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bitpos = pin & 0x1F;
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putreg32(getreg32(GPIO_INT_PEND_CLR_REG + addr) | (1 << bitpos), GPIO_INT_PEND_CLR_REG + addr); // pending clear
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}
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uint32_t gpio_set(PinName pin)
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{
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int bit;
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bit = pin % 32;
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return (1 << bit);
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}
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void gpio_init(gpio_t *obj, PinName pin)
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{
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int idx;
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int bit;
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if (pin == NC || pin > P72) {
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obj->reg_out = NULL;
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obj->pin = NC;
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return;
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}
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idx = pin / 32;
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bit = pin % 32;
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obj->pin = pin;
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obj->mask = (1 << bit);
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obj->reg_out = (unsigned int *)(GPIO_OUT_REG + (idx * 4));
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obj->reg_dir = (unsigned int *)(GPIO_CON_REG + (idx * 4));
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obj->reg_in = (unsigned int *)(GPIO_IN_REG + (idx * 4));
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if (pin >= P00 && pin <= P72) {
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// Set GPIO pin set as GENERAL GPIO
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s5js100_configgpio(GPIO_DEFAULT_CONFIG | pin << GPIO_PIN_SHIFT);
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}
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}
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void gpio_mode(gpio_t *obj, PinMode mode)
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{
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enum gpio_id_ id = (enum gpio_id_)obj->pin;
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if (obj->reg_out == NULL) {
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return;
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}
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//pin_mode(obj->pin, mode);
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if (mode == PullUp) {
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gpio_pin_mode(obj->pin, mode);
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gpio_set_pupd(id, GPIO_PULL_UP);
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}
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if (mode == PullDown) {
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gpio_pin_mode(obj->pin, mode);
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gpio_set_pupd(id, GPIO_PULL_DOWN);
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}
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}
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void gpio_dir(gpio_t *obj, PinDirection direction)
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{
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if (obj->reg_out == NULL) {
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return;
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}
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if (direction == PIN_INPUT) {
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*(obj->reg_dir) |= obj->mask;
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} else if (direction == PIN_OUTPUT) {
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*(obj->reg_dir) &= ~(obj->mask);
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}
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}
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int gpio_is_connected(const gpio_t *obj)
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{
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if (obj->pin != (PinName)NC) {
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return 1;
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} else {
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return 0;
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}
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}
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