mirror of https://github.com/ARMmbed/mbed-os.git
127 lines
5.7 KiB
C
127 lines
5.7 KiB
C
/****************************************************************************
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*
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* Copyright 2020 Samsung Electronics All Rights Reserved.
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing,
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* software distributed under the License is distributed on an
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* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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* either express or implied. See the License for the specific
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* language governing permissions and limitations under the License.
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*
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****************************************************************************/
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#ifndef SSS_MAP_H
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#define SSS_MAP_H
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/*************** Include Files ********************************************/
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/*************** Assertions ***********************************************/
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/*************** Definitions / Macros *************************************/
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#define SSS_CMD_GET_INFO (0x101)
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#define SSS_CMD_SUCCESS (0xA1)
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#define SSS_CMD_FAIL (0xF1)
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#define SSS_SRAM_LOCK_EN (0x01)
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#define SSS_DEBUG_LOCK_EN (0x08)
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/*************** New Data Types (Basic Data Types) ***********************/
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/*************** New Data Types *******************************************/
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/*************** Constants ************************************************/
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/*************** Variable declarations ************************************/
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/*************** Functions ***********************************************/
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/////////////////////////////////////////////////////////
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// SSS Address in S5J_S100 and S5JT100 //////////////////
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/////////////////////////////////////////////////////////
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#if defined(TARGET_S5JS100)
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#define SSS_REG_BASE (0x83100000)
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#define MAILBOX_BASE (0x83110000)
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#define SSS_SRAM_BASE (0x83108000)
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#define SSS_TRNG_BASE (0x83180000)
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#endif
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#if defined(TARGET_S3JT100)
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#define SSS_REG_BASE (0x400C0000)
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#define MAILBOX_BASE (0x400E0000)
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#define SSS_SRAM_BASE (0x400C8000)
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#define SSS_TRNG_BASE (0x400C1400)
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#endif
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/////////////////////////////////////////////////////////
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// SSS MAP //////////////////////////////////////////////
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/////////////////////////////////////////////////////////
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#define SSS_FEEDER_BASE (SSS_REG_BASE)
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#define SSS_DATA_BASE (SSS_SRAM_BASE + 0x6F00)
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#define SSS_CM0_LP_CON (*(volatile unsigned int *)(SSS_FEEDER_BASE + 0x001C))
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#define SSS_LOW_POWER_MODE_EN (1<<0)
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#define SSS_CM0_RESET (*(volatile unsigned int *)(MAILBOX_BASE + 0x0004))
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#define SSS_CM0_HRESET (1<<0)
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#define SSS_CM0_SRAM_ACCESS_CONTROL (*(volatile unsigned int *)(MAILBOX_BASE + 0x0008))
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#define SSS_CM0_DEBUG_CONTROL (*(volatile unsigned int *)(MAILBOX_BASE + 0x0038))
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#define SSS_MB_STATUS (*(volatile unsigned int *)(MAILBOX_BASE + 0x0000))
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#define SSS_CM0_BUSY (1<<0)
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#define SSS_CTRL_FIELD_BASE (MAILBOX_BASE + 0x0100)
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#define SSS_DATA_FIELD_BASE (MAILBOX_BASE + 0x0110)
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#define SSS_TRNG_CLKDIV (*(volatile unsigned int *)(SSS_REG_BASE + 0x1400))
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#define SSS_TRNG_STARTUP_CTRL (*(volatile unsigned int *)(SSS_REG_BASE + 0x144C))
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#define SSS_STARTUP_HTPASS (1<<0)
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#define SSS_STARTUP_HTPASS_CLR (1<<0)
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#define SSS_TRNG_CTRL (*(volatile unsigned int *)(SSS_REG_BASE + 0x1420))
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#define SSS_RNGEN (0x80000000)
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#define SSS_TRNG_TEST_CTRL (*(volatile unsigned int *)(SSS_REG_BASE + 0x1440))
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#define SSS_HTEN (1<<1)
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#define SSS_TRNG_TEST_DONE (*(volatile unsigned int *)(SSS_REG_BASE + 0x1460))
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#define SSS_HTDONE (1<<1)
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#define SSS_KATDONE (1<<2)
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#define SSS_TRNG_TEST_STAT (*(volatile unsigned int *)(SSS_REG_BASE + 0x1444))
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#define SSS_HTERR (1<<2)
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#define SSS_KAT_PPERR (1<<3)
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#define SSS_KAT_CRNGTERR (1<<4)
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#define SSS_TRNG_FIFO_CTRL (*(volatile unsigned int *)(SSS_REG_BASE + 0x1450))
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#define SSS_GEN_1_BYTE (1)
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#define SSS_GEN_2_BYTE (2)
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#define SSS_GEN_32_BYTE (32)
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#if defined(TARGET_S5JS100)
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#ifdef OTP_BANK
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#define OTP_BASE (0x80000000)
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#define SSS_ROOT_ENCRYPTION_KEY_BASE (OTP_BASE + 0x000)
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#define SSS_ROOT_PRIVATE_KEY_BASE (OTP_BASE + 0x020)
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#define SSS_FW_ENCRYPTION_KEY_BASE (OTP_BASE + 0x080)
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#define SSS_KM_DIAG_DISABLE (OTP_BASE + 0x0A0)
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#define SSS_CM0_DEBUG_DISABLE (OTP_BASE + 0x0A4)
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#define SSS_CM0_SRAM_BOOT_DISABLE (OTP_BASE + 0x0A8)
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#define SSS_CM0_SRAM_READ_DISABLE (OTP_BASE + 0x0AC)
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#define SSS_CM0_ANTI_ROLLBACK_COUNT (OTP_BASE + 0x0B0)
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#define SSS_CM0_SECURE_BOOT_KEY_BASE (OTP_BASE + 0x0C0)
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#define SSS_TRANSFER_KEY1_BASE (OTP_BASE + 0x100)
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#define SSS_TRANSFER_KEY2_BASE (OTP_BASE + 0x110)
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#define SSS_TRANSFER_KEY3_BASE (OTP_BASE + 0x120)
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#define SSS_TRANSFER_KEY4_BASE (OTP_BASE + 0x130)
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#define PUF_KEY_BASE (OTP_BASE + 0x140)
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#define PUF_KEY_VALID (OTP_BASE + 0x160)
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#define SSS_SW_POR (OTP_BASE + 0x200)
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#endif //OTP_BANK
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#endif //TARGET_S5JS100
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#endif /* SSS_MAP_H */
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