mirror of https://github.com/ARMmbed/mbed-os.git
437 lines
18 KiB
C++
437 lines
18 KiB
C++
/*
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* Copyright (c) 2019, Arm Limited and affiliates.
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#if !DEVICE_SPI
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#error [NOT_SUPPORTED] SPI not supported for this target
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#elif !COMPONENT_FPGA_CI_TEST_SHIELD
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#error [NOT_SUPPORTED] FPGA CI Test Shield is needed to run this test
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#elif !defined(TARGET_FF_ARDUINO) && !defined(MBED_CONF_TARGET_DEFAULT_FORM_FACTOR)
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#error [NOT_SUPPORTED] Test not supported for this form factor
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#else
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#include "utest/utest.h"
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#include "unity/unity.h"
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#include "greentea-client/test_env.h"
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#include "mbed.h"
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#include "SPIMasterTester.h"
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#include "pinmap.h"
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#include "hal/static_pinmap.h"
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#include "test_utils.h"
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#include "spi_fpga_test.h"
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using namespace utest::v1;
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typedef enum {
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TRANSFER_SPI_MASTER_WRITE_SYNC,
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TRANSFER_SPI_MASTER_BLOCK_WRITE_SYNC,
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TRANSFER_SPI_MASTER_TRANSFER_ASYNC
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} transfer_type_t;
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typedef enum {
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BUFFERS_COMMON, // common case rx/tx buffers are defined and have the same size
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BUFFERS_TX_GT_RX, // tx buffer length is greater than rx buffer length
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BUFFERS_TX_LT_RX, // tx buffer length is less than rx buffer length
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BUFFERS_TX_ONE_SYM, // one symbol only is transmitted in both directions
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} test_buffers_t;
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#define FREQ_200_KHZ (200000ull)
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#define FREQ_500_KHZ (500000)
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#define FREQ_1_MHZ (1000000)
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#define FREQ_2_MHZ (2000000)
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#define FREQ_10_MHZ (10000000ull)
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#define FREQ_MIN ((uint32_t)0)
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#define FREQ_MAX ((uint32_t)-1)
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#define FILL_SYM (0xF5F5F5F5)
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#define DUMMY_SYM (0xD5D5D5D5)
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#define SS_ASSERT (0)
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#define SS_DEASSERT (!(SS_ASSERT))
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#define TEST_CAPABILITY_BIT(MASK, CAP) ((1 << CAP) & (MASK))
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const int TRANSFER_COUNT = 300;
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SPIMasterTester tester(DefaultFormFactor::pins(), DefaultFormFactor::restricted_pins());
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spi_t spi;
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static volatile bool async_trasfer_done;
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#if DEVICE_SPI_ASYNCH
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void spi_async_handler()
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{
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int event = spi_irq_handler_asynch(&spi);
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if (event & SPI_EVENT_COMPLETE) {
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async_trasfer_done = true;
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}
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}
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#endif
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/* Function finds SS pin for manual SS handling. */
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static PinName find_ss_pin(PinName mosi, PinName miso, PinName sclk)
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{
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const PinList *ff_pins_list = pinmap_ff_default_pins();
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const PinList *restricted_pins_list = pinmap_restricted_pins();
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uint32_t cs_pin_idx;
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for (cs_pin_idx = 0; cs_pin_idx < ff_pins_list->count; cs_pin_idx++) {
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if (ff_pins_list->pins[cs_pin_idx] == mosi ||
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ff_pins_list->pins[cs_pin_idx] == miso ||
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ff_pins_list->pins[cs_pin_idx] == sclk) {
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continue;
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}
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bool restricted_pin = false;
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for (uint32_t i = 0; i < restricted_pins_list->count ; i++) {
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if (ff_pins_list->pins[cs_pin_idx] == restricted_pins_list->pins[i]) {
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restricted_pin = true;
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}
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}
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if (restricted_pin) {
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continue;
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} else {
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break;
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}
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}
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PinName ssel = (cs_pin_idx == ff_pins_list->count ? NC : ff_pins_list->pins[cs_pin_idx]);
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TEST_ASSERT_MESSAGE(ssel != NC, "Unable to find pin for Chip Select");
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return ssel;
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}
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/* Function handles ss line if ss is specified. */
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static void handle_ss(DigitalOut *ss, bool select)
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{
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if (ss) {
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if (select) {
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*ss = SS_ASSERT;
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} else {
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*ss = SS_DEASSERT;
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}
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}
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}
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/* Auxiliary function to check platform capabilities against test case. */
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static bool check_capabilities(const spi_capabilities_t *capabilities, SPITester::SpiMode spi_mode, uint32_t sym_size, transfer_type_t transfer_type, uint32_t frequency, test_buffers_t test_buffers)
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{
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// Symbol size
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if (!TEST_CAPABILITY_BIT(capabilities->word_length, (sym_size - 1))) {
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utest_printf("\n<Specified symbol size is not supported on this platform> skipped. ");
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return false;
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}
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// SPI clock mode
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if (!TEST_CAPABILITY_BIT(capabilities->clk_modes, spi_mode)) {
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utest_printf("\n<Specified spi clock mode is not supported on this platform> skipped. ");
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return false;
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}
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// Frequency
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if (frequency != FREQ_MAX && frequency != FREQ_MIN && frequency < capabilities->minimum_frequency && frequency > capabilities->maximum_frequency) {
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utest_printf("\n<Specified frequency is not supported on this platform> skipped. ");
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return false;
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}
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// Async mode
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if (transfer_type == TRANSFER_SPI_MASTER_TRANSFER_ASYNC && capabilities->async_mode == false) {
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utest_printf("\n<Async mode is not supported on this platform> skipped. ");
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return false;
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}
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if ((test_buffers == BUFFERS_TX_GT_RX || test_buffers == BUFFERS_TX_LT_RX) && capabilities->tx_rx_buffers_equal_length == true) {
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utest_printf("\n<RX length != TX length is not supported on this platform> skipped. ");
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return false;
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}
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return true;
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}
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void fpga_spi_test_init_free(PinName mosi, PinName miso, PinName sclk, PinName ssel)
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{
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spi_init(&spi, mosi, miso, sclk, ssel);
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spi_format(&spi, 8, 0, 0);
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spi_frequency(&spi, 1000000);
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spi_free(&spi);
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}
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void fpga_spi_test_init_free_cs_nc(PinName mosi, PinName miso, PinName sclk)
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{
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spi_init(&spi, mosi, miso, sclk, NC);
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spi_format(&spi, 8, 0, 0);
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spi_frequency(&spi, 1000000);
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spi_free(&spi);
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}
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void fpga_spi_test_init_free_cs_nc_miso_nc_mosi_nc(PinName mosi, PinName miso, PinName sclk)
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{
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utest_printf("\nTesting: MOSI = NC. ");
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spi_init(&spi, NC, miso, sclk, NC);
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spi_format(&spi, 8, 0, 0);
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spi_frequency(&spi, 1000000);
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spi_free(&spi);
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utest_printf("Testing: MISO = NC. ");
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spi_init(&spi, mosi, NC, sclk, NC);
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spi_format(&spi, 8, 0, 0);
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spi_frequency(&spi, 1000000);
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spi_free(&spi);
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}
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void fpga_spi_test_common(PinName mosi, PinName miso, PinName sclk, PinName ssel, SPITester::SpiMode spi_mode, uint32_t sym_size, transfer_type_t transfer_type, uint32_t frequency, test_buffers_t test_buffers, bool auto_ss, bool init_direct)
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{
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spi_capabilities_t capabilities;
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uint32_t freq = frequency;
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uint32_t tx_cnt = TRANSFER_COUNT;
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uint32_t rx_cnt = TRANSFER_COUNT;
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uint8_t fill_symbol = (uint8_t)FILL_SYM;
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PinName ss_pin = (auto_ss ? ssel : NC);
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DigitalOut *ss = NULL;
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spi_get_capabilities(ssel, false, &capabilities);
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if (check_capabilities(&capabilities, spi_mode, sym_size, transfer_type, frequency, test_buffers) == false) {
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return;
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}
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uint32_t sym_mask = ((1 << sym_size) - 1);
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switch (frequency) {
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case (FREQ_MIN):
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freq = capabilities.minimum_frequency;
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break;
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case (FREQ_MAX):
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freq = capabilities.maximum_frequency;
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break;
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default:
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break;
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}
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switch (test_buffers) {
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case (BUFFERS_COMMON):
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// nothing to change
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break;
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case (BUFFERS_TX_GT_RX):
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rx_cnt /= 2;
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break;
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case (BUFFERS_TX_LT_RX):
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tx_cnt /= 2;
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break;
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case (BUFFERS_TX_ONE_SYM):
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tx_cnt = 1;
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rx_cnt = 1;
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break;
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default:
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break;
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}
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// Remap pins for test
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tester.reset();
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tester.pin_map_set(mosi, MbedTester::LogicalPinSPIMosi);
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tester.pin_map_set(miso, MbedTester::LogicalPinSPIMiso);
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tester.pin_map_set(sclk, MbedTester::LogicalPinSPISclk);
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tester.pin_map_set(ssel, MbedTester::LogicalPinSPISsel);
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// Manually handle SS pin
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if (!auto_ss) {
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ss = new DigitalOut(ssel, SS_DEASSERT);
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}
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if (init_direct) {
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const spi_pinmap_t pinmap = get_spi_pinmap(mosi, miso, sclk, ss_pin);
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spi_init_direct(&spi, &pinmap);
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} else {
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spi_init(&spi, mosi, miso, sclk, ss_pin);
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}
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spi_format(&spi, sym_size, spi_mode, 0);
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spi_frequency(&spi, freq);
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// Configure spi_slave module
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tester.set_mode(spi_mode);
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tester.set_bit_order(SPITester::MSBFirst);
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tester.set_sym_size(sym_size);
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// Reset tester stats and select SPI
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tester.peripherals_reset();
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tester.select_peripheral(SPITester::PeripheralSPI);
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uint32_t checksum = 0;
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uint32_t sym_count = TRANSFER_COUNT;
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int result = 0;
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uint8_t tx_buf[TRANSFER_COUNT] = {0};
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uint8_t rx_buf[TRANSFER_COUNT] = {0};
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// Send and receive test data
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switch (transfer_type) {
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case TRANSFER_SPI_MASTER_WRITE_SYNC:
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handle_ss(ss, true);
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for (int i = 0; i < TRANSFER_COUNT; i++) {
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uint32_t data = spi_master_write(&spi, (0 - i) & sym_mask);
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TEST_ASSERT_EQUAL(i & sym_mask, data);
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checksum += (0 - i) & sym_mask;
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}
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handle_ss(ss, false);
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break;
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case TRANSFER_SPI_MASTER_BLOCK_WRITE_SYNC:
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for (int i = 0; i < TRANSFER_COUNT; i++) {
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tx_buf[i] = (0 - i) & sym_mask;
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rx_buf[i] = 0xFF;
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switch (test_buffers) {
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case (BUFFERS_COMMON):
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case (BUFFERS_TX_GT_RX):
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checksum += ((0 - i) & sym_mask);
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break;
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case (BUFFERS_TX_LT_RX):
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if (i < tx_cnt) {
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checksum += ((0 - i) & sym_mask);
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} else {
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checksum += (fill_symbol & sym_mask);
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}
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break;
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case (BUFFERS_TX_ONE_SYM):
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tx_buf[0] = 0xAA;
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checksum = 0xAA;
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sym_count = 1;
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break;
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default:
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break;
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}
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}
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handle_ss(ss, true);
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result = spi_master_block_write(&spi, (const char *)tx_buf, tx_cnt, (char *)rx_buf, rx_cnt, 0xF5);
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handle_ss(ss, false);
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for (int i = 0; i < rx_cnt; i++) {
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TEST_ASSERT_EQUAL(i & sym_mask, rx_buf[i]);
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}
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for (int i = rx_cnt; i < TRANSFER_COUNT; i++) {
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TEST_ASSERT_EQUAL(0xFF, rx_buf[i]);
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}
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TEST_ASSERT_EQUAL(sym_count, result);
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break;
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#if DEVICE_SPI_ASYNCH
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case TRANSFER_SPI_MASTER_TRANSFER_ASYNC:
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for (int i = 0; i < TRANSFER_COUNT; i++) {
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tx_buf[i] = (0 - i) & sym_mask;
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checksum += (0 - i) & sym_mask;
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rx_buf[i] = 0xAA;
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}
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async_trasfer_done = false;
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handle_ss(ss, true);
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spi_master_transfer(&spi, tx_buf, TRANSFER_COUNT, rx_buf, TRANSFER_COUNT, 8, (uint32_t)spi_async_handler, SPI_EVENT_COMPLETE, DMA_USAGE_NEVER);
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while (!async_trasfer_done);
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handle_ss(ss, false);
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for (int i = 0; i < TRANSFER_COUNT; i++) {
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TEST_ASSERT_EQUAL(i & sym_mask, rx_buf[i]);
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}
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break;
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#endif
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default:
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TEST_ASSERT_MESSAGE(0, "Unsupported transfer type.");
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break;
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}
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// Verify that the transfer was successful
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TEST_ASSERT_EQUAL(sym_count, tester.get_transfer_count());
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TEST_ASSERT_EQUAL(checksum, tester.get_receive_checksum());
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spi_free(&spi);
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tester.reset();
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}
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template<SPITester::SpiMode spi_mode, uint32_t sym_size, transfer_type_t transfer_type, uint32_t frequency, test_buffers_t test_buffers, bool auto_ss, bool init_direct>
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void fpga_spi_test_common(PinName mosi, PinName miso, PinName sclk, PinName ssel)
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{
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fpga_spi_test_common(mosi, miso, sclk, ssel, spi_mode, sym_size, transfer_type, frequency, test_buffers, auto_ss, init_direct);
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}
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template<SPITester::SpiMode spi_mode, uint32_t sym_size, transfer_type_t transfer_type, uint32_t frequency, test_buffers_t test_buffers, bool auto_ss, bool init_direct>
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void fpga_spi_test_common_no_ss(PinName mosi, PinName miso, PinName sclk)
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{
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PinName ssel = find_ss_pin(mosi, miso, sclk);
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fpga_spi_test_common(mosi, miso, sclk, ssel, spi_mode, sym_size, transfer_type, frequency, test_buffers, auto_ss, init_direct);
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}
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Case cases[] = {
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// This will be run for all pins
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Case("SPI - init/free test all pins", all_ports<SPIPort, DefaultFormFactor, fpga_spi_test_init_free>),
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Case("SPI - init/free test all pins (CS == NC)", all_ports<SPINoCSPort, DefaultFormFactor, fpga_spi_test_init_free_cs_nc>),
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Case("SPI - init/free test all pins (CS == NC, MISO/MOSI == NC)", one_peripheral<SPINoCSPort, DefaultFormFactor, fpga_spi_test_init_free_cs_nc_miso_nc_mosi_nc>),
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// This will be run for all peripherals
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Case("SPI - basic test", all_peripherals<SPINoCSPort, DefaultFormFactor, fpga_spi_test_common_no_ss<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ, BUFFERS_COMMON, false, false> >),
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Case("SPI - basic test (direct init)", all_peripherals<SPINoCSPort, DefaultFormFactor, fpga_spi_test_common_no_ss<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ, BUFFERS_COMMON, false, true> >),
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// This will be run for single pin configuration
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Case("SPI - mode testing (MODE_1)", one_peripheral<SPINoCSPort, DefaultFormFactor, fpga_spi_test_common_no_ss<SPITester::Mode1, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ, BUFFERS_COMMON, false, false> >),
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Case("SPI - mode testing (MODE_2)", one_peripheral<SPINoCSPort, DefaultFormFactor, fpga_spi_test_common_no_ss<SPITester::Mode2, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ, BUFFERS_COMMON, false, false> >),
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Case("SPI - mode testing (MODE_3)", one_peripheral<SPINoCSPort, DefaultFormFactor, fpga_spi_test_common_no_ss<SPITester::Mode3, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ, BUFFERS_COMMON, false, false> >),
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Case("SPI - symbol size testing (4)", one_peripheral<SPINoCSPort, DefaultFormFactor, fpga_spi_test_common_no_ss<SPITester::Mode0, 4, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ, BUFFERS_COMMON, false, false> >),
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Case("SPI - symbol size testing (12)", one_peripheral<SPINoCSPort, DefaultFormFactor, fpga_spi_test_common_no_ss<SPITester::Mode0, 12, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ, BUFFERS_COMMON, false, false> >),
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Case("SPI - symbol size testing (16)", one_peripheral<SPINoCSPort, DefaultFormFactor, fpga_spi_test_common_no_ss<SPITester::Mode0, 16, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ, BUFFERS_COMMON, false, false> >),
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Case("SPI - symbol size testing (24)", one_peripheral<SPINoCSPort, DefaultFormFactor, fpga_spi_test_common_no_ss<SPITester::Mode0, 24, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ, BUFFERS_COMMON, false, false> >),
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Case("SPI - symbol size testing (32)", one_peripheral<SPINoCSPort, DefaultFormFactor, fpga_spi_test_common_no_ss<SPITester::Mode0, 32, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ, BUFFERS_COMMON, false, false> >),
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Case("SPI - buffers tx > rx", one_peripheral<SPINoCSPort, DefaultFormFactor, fpga_spi_test_common_no_ss<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_BLOCK_WRITE_SYNC, FREQ_1_MHZ, BUFFERS_TX_GT_RX, false, false> >),
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Case("SPI - buffers tx < rx", one_peripheral<SPINoCSPort, DefaultFormFactor, fpga_spi_test_common_no_ss<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_BLOCK_WRITE_SYNC, FREQ_1_MHZ, BUFFERS_TX_LT_RX, false, false> >),
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Case("SPI - frequency testing (200 kHz)", one_peripheral<SPINoCSPort, DefaultFormFactor, fpga_spi_test_common_no_ss<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_200_KHZ, BUFFERS_COMMON, false, false> >),
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Case("SPI - frequency testing (2 MHz)", one_peripheral<SPINoCSPort, DefaultFormFactor, fpga_spi_test_common_no_ss<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_2_MHZ, BUFFERS_COMMON, false, false> >),
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Case("SPI - frequency testing (capabilities min)", one_peripheral<SPINoCSPort, DefaultFormFactor, fpga_spi_test_common_no_ss<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_MIN, BUFFERS_COMMON, false, false> >),
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Case("SPI - frequency testing (capabilities max)", one_peripheral<SPINoCSPort, DefaultFormFactor, fpga_spi_test_common_no_ss<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_MAX, BUFFERS_COMMON, false, false> >),
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Case("SPI - block write", one_peripheral<SPINoCSPort, DefaultFormFactor, fpga_spi_test_common_no_ss<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_BLOCK_WRITE_SYNC, FREQ_1_MHZ, BUFFERS_COMMON, false, false> >),
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Case("SPI - block write(one sym)", one_peripheral<SPINoCSPort, DefaultFormFactor, fpga_spi_test_common_no_ss<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_BLOCK_WRITE_SYNC, FREQ_1_MHZ, BUFFERS_TX_ONE_SYM, false, false> >),
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Case("SPI - hardware ss handling", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ, BUFFERS_COMMON, true, false> >),
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Case("SPI - hardware ss handling(block)", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_BLOCK_WRITE_SYNC, FREQ_1_MHZ, BUFFERS_COMMON, true, false> >),
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#if DEVICE_SPI_ASYNCH
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Case("SPI - async mode (sw ss)", one_peripheral<SPINoCSPort, DefaultFormFactor, fpga_spi_test_common_no_ss<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_TRANSFER_ASYNC, FREQ_1_MHZ, BUFFERS_COMMON, false, false> >),
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Case("SPI - async mode (hw ss)", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_TRANSFER_ASYNC, FREQ_1_MHZ, BUFFERS_COMMON, true, false> >)
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#endif
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};
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utest::v1::status_t greentea_test_setup(const size_t number_of_cases)
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{
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GREENTEA_SETUP(60, "default_auto");
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return greentea_test_setup_handler(number_of_cases);
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}
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Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler);
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int main()
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{
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Harness::run(specification);
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}
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#endif /* !DEVICE_SPI */
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