mirror of https://github.com/ARMmbed/mbed-os.git
108 lines
4.5 KiB
C
108 lines
4.5 KiB
C
/***************************************************************************//**
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* \file cyip_smartio.h
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*
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* \brief
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* SMARTIO IP definitions
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*
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* \note
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* Generator version: 1.2.0.117
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* Database revision: rev#1034984
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*
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********************************************************************************
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* \copyright
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* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
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* SPDX-License-Identifier: Apache-2.0
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*******************************************************************************/
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#ifndef _CYIP_SMARTIO_H_
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#define _CYIP_SMARTIO_H_
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#include "cyip_headers.h"
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/*******************************************************************************
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* SMARTIO
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*******************************************************************************/
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#define SMARTIO_PRT_SECTION_SIZE 0x00000100UL
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#define SMARTIO_SECTION_SIZE 0x00010000UL
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/**
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* \brief Programmable IO port registers (SMARTIO_PRT)
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*/
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typedef struct {
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__IOM uint32_t CTL; /*!< 0x00000000 Control register */
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__IM uint32_t RESERVED[3];
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__IOM uint32_t SYNC_CTL; /*!< 0x00000010 Synchronization control register */
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__IM uint32_t RESERVED1[3];
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__IOM uint32_t LUT_SEL[8]; /*!< 0x00000020 LUT component input selection */
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__IOM uint32_t LUT_CTL[8]; /*!< 0x00000040 LUT component control register */
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__IM uint32_t RESERVED2[24];
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__IOM uint32_t DU_SEL; /*!< 0x000000C0 Data unit component input selection */
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__IOM uint32_t DU_CTL; /*!< 0x000000C4 Data unit component control register */
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__IM uint32_t RESERVED3[10];
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__IOM uint32_t DATA; /*!< 0x000000F0 Data register */
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__IM uint32_t RESERVED4[3];
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} SMARTIO_PRT_Type; /*!< Size = 256 (0x100) */
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/**
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* \brief Programmable IO configuration (SMARTIO)
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*/
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typedef struct {
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SMARTIO_PRT_Type PRT[128]; /*!< 0x00000000 Programmable IO port registers */
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} SMARTIO_Type; /*!< Size = 32768 (0x8000) */
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/* SMARTIO_PRT.CTL */
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#define SMARTIO_PRT_CTL_BYPASS_Pos 0UL
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#define SMARTIO_PRT_CTL_BYPASS_Msk 0xFFUL
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#define SMARTIO_PRT_CTL_CLOCK_SRC_Pos 8UL
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#define SMARTIO_PRT_CTL_CLOCK_SRC_Msk 0x1F00UL
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#define SMARTIO_PRT_CTL_HLD_OVR_Pos 24UL
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#define SMARTIO_PRT_CTL_HLD_OVR_Msk 0x1000000UL
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#define SMARTIO_PRT_CTL_PIPELINE_EN_Pos 25UL
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#define SMARTIO_PRT_CTL_PIPELINE_EN_Msk 0x2000000UL
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#define SMARTIO_PRT_CTL_ENABLED_Pos 31UL
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#define SMARTIO_PRT_CTL_ENABLED_Msk 0x80000000UL
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/* SMARTIO_PRT.SYNC_CTL */
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#define SMARTIO_PRT_SYNC_CTL_IO_SYNC_EN_Pos 0UL
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#define SMARTIO_PRT_SYNC_CTL_IO_SYNC_EN_Msk 0xFFUL
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#define SMARTIO_PRT_SYNC_CTL_CHIP_SYNC_EN_Pos 8UL
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#define SMARTIO_PRT_SYNC_CTL_CHIP_SYNC_EN_Msk 0xFF00UL
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/* SMARTIO_PRT.LUT_SEL */
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#define SMARTIO_PRT_LUT_SEL_LUT_TR0_SEL_Pos 0UL
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#define SMARTIO_PRT_LUT_SEL_LUT_TR0_SEL_Msk 0xFUL
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#define SMARTIO_PRT_LUT_SEL_LUT_TR1_SEL_Pos 8UL
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#define SMARTIO_PRT_LUT_SEL_LUT_TR1_SEL_Msk 0xF00UL
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#define SMARTIO_PRT_LUT_SEL_LUT_TR2_SEL_Pos 16UL
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#define SMARTIO_PRT_LUT_SEL_LUT_TR2_SEL_Msk 0xF0000UL
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/* SMARTIO_PRT.LUT_CTL */
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#define SMARTIO_PRT_LUT_CTL_LUT_Pos 0UL
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#define SMARTIO_PRT_LUT_CTL_LUT_Msk 0xFFUL
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#define SMARTIO_PRT_LUT_CTL_LUT_OPC_Pos 8UL
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#define SMARTIO_PRT_LUT_CTL_LUT_OPC_Msk 0x300UL
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/* SMARTIO_PRT.DU_SEL */
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#define SMARTIO_PRT_DU_SEL_DU_TR0_SEL_Pos 0UL
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#define SMARTIO_PRT_DU_SEL_DU_TR0_SEL_Msk 0xFUL
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#define SMARTIO_PRT_DU_SEL_DU_TR1_SEL_Pos 8UL
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#define SMARTIO_PRT_DU_SEL_DU_TR1_SEL_Msk 0xF00UL
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#define SMARTIO_PRT_DU_SEL_DU_TR2_SEL_Pos 16UL
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#define SMARTIO_PRT_DU_SEL_DU_TR2_SEL_Msk 0xF0000UL
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#define SMARTIO_PRT_DU_SEL_DU_DATA0_SEL_Pos 24UL
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#define SMARTIO_PRT_DU_SEL_DU_DATA0_SEL_Msk 0x3000000UL
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#define SMARTIO_PRT_DU_SEL_DU_DATA1_SEL_Pos 28UL
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#define SMARTIO_PRT_DU_SEL_DU_DATA1_SEL_Msk 0x30000000UL
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/* SMARTIO_PRT.DU_CTL */
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#define SMARTIO_PRT_DU_CTL_DU_SIZE_Pos 0UL
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#define SMARTIO_PRT_DU_CTL_DU_SIZE_Msk 0x7UL
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#define SMARTIO_PRT_DU_CTL_DU_OPC_Pos 8UL
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#define SMARTIO_PRT_DU_CTL_DU_OPC_Msk 0xF00UL
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/* SMARTIO_PRT.DATA */
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#define SMARTIO_PRT_DATA_DATA_Pos 0UL
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#define SMARTIO_PRT_DATA_DATA_Msk 0xFFUL
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#endif /* _CYIP_SMARTIO_H_ */
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/* [] END OF FILE */
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