mirror of https://github.com/ARMmbed/mbed-os.git
458 lines
27 KiB
C
458 lines
27 KiB
C
/***************************************************************************//**
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* \file cyip_sflash.h
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*
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* \brief
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* SFLASH IP definitions
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*
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* \note
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* Generator version: 1.2.0.117
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* Database revision: rev#1034984
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*
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********************************************************************************
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* \copyright
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* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
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* SPDX-License-Identifier: Apache-2.0
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*******************************************************************************/
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#ifndef _CYIP_SFLASH_H_
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#define _CYIP_SFLASH_H_
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#include "cyip_headers.h"
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/*******************************************************************************
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* SFLASH
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*******************************************************************************/
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#define SFLASH_SECTION_SIZE 0x00008000UL
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/**
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* \brief FLASH Supervisory Region (SFLASH)
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*/
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typedef struct {
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__IM uint8_t RESERVED;
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__IOM uint8_t SI_REVISION_ID; /*!< 0x00000001 Indicates Silicon Revision ID of the device */
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__IOM uint16_t SILICON_ID; /*!< 0x00000002 Indicates Silicon ID of the device */
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__IM uint32_t RESERVED1[2];
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__IOM uint16_t FAMILY_ID; /*!< 0x0000000C Indicates Family ID of the device */
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__IM uint16_t RESERVED2[761];
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__IOM uint8_t DIE_LOT[3]; /*!< 0x00000600 Lot Number (3 bytes) */
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__IOM uint8_t DIE_WAFER; /*!< 0x00000603 Wafer Number */
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__IOM uint8_t DIE_X; /*!< 0x00000604 X Position on Wafer, CRI Pass/Fail Bin */
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__IOM uint8_t DIE_Y; /*!< 0x00000605 Y Position on Wafer, CHI Pass/Fail Bin */
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__IOM uint8_t DIE_SORT; /*!< 0x00000606 Sort1/2/3 Pass/Fail Bin */
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__IOM uint8_t DIE_MINOR; /*!< 0x00000607 Minor Revision Number */
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__IOM uint8_t DIE_DAY; /*!< 0x00000608 Day number */
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__IOM uint8_t DIE_MONTH; /*!< 0x00000609 Month number */
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__IOM uint8_t DIE_YEAR; /*!< 0x0000060A Year number */
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__IM uint8_t RESERVED3[61];
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__IOM uint16_t SAR_TEMP_MULTIPLIER; /*!< 0x00000648 SAR Temperature Sensor Multiplication Factor */
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__IOM uint16_t SAR_TEMP_OFFSET; /*!< 0x0000064A SAR Temperature Sensor Offset */
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__IM uint32_t RESERVED4[8];
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__IOM uint32_t CSP_PANEL_ID; /*!< 0x0000066C CSP Panel Id to record panel ID of CSP die */
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__IM uint32_t RESERVED5[52];
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__IOM uint8_t LDO_0P9V_TRIM; /*!< 0x00000740 LDO_0P9V_TRIM */
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__IOM uint8_t LDO_1P1V_TRIM; /*!< 0x00000741 LDO_1P1V_TRIM */
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__IM uint16_t RESERVED6[95];
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__IOM uint32_t BLE_DEVICE_ADDRESS[128]; /*!< 0x00000800 BLE_DEVICE_ADDRESS */
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__IOM uint32_t USER_FREE_ROW1[128]; /*!< 0x00000A00 USER_FREE_ROW1 */
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__IOM uint32_t USER_FREE_ROW2[128]; /*!< 0x00000C00 USER_FREE_ROW2 */
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__IOM uint32_t USER_FREE_ROW3[128]; /*!< 0x00000E00 USER_FREE_ROW3 */
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__IM uint32_t RESERVED7[302];
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__IOM uint8_t DEVICE_UID[16]; /*!< 0x000014B8 Unique Identifier Number for each device */
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__IOM uint8_t MASTER_KEY[16]; /*!< 0x000014C8 Master key to change other keys */
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__IOM uint32_t STANDARD_SMPU_STRUCT_SLAVE_ADDR[16]; /*!< 0x000014D8 Standard SMPU STRUCT Slave Address value */
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__IOM uint32_t STANDARD_SMPU_STRUCT_SLAVE_ATTR[16]; /*!< 0x00001518 Standard SMPU STRUCT Slave Attribute value */
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__IOM uint32_t STANDARD_SMPU_STRUCT_MASTER_ATTR[16]; /*!< 0x00001558 Standard SMPU STRUCT Master Attribute value */
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__IOM uint32_t STANDARD_MPU_STRUCT[16]; /*!< 0x00001598 Standard MPU STRUCT */
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__IOM uint32_t STANDARD_PPU_STRUCT[16]; /*!< 0x000015D8 Standard PPU STRUCT */
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__IM uint32_t RESERVED8[122];
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__IOM uint16_t PILO_FREQ_STEP; /*!< 0x00001800 Resolution step for PILO at class in BCD format */
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__IM uint16_t RESERVED9;
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__IOM uint32_t CSDV2_CSD0_ADC_VREF0; /*!< 0x00001804 CSD 1p2 & 1p6 voltage levels for accuracy */
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__IOM uint32_t CSDV2_CSD0_ADC_VREF1; /*!< 0x00001808 CSD 2p3 & 0p8 voltage levels for accuracy */
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__IOM uint32_t CSDV2_CSD0_ADC_VREF2; /*!< 0x0000180C CSD calibration spare voltage level for accuracy */
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__IOM uint32_t PWR_TRIM_WAKE_CTL; /*!< 0x00001810 Wakeup delay */
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__IM uint16_t RESERVED10;
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__IOM uint16_t RADIO_LDO_TRIMS; /*!< 0x00001816 Radio LDO Trims */
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__IOM uint32_t CPUSS_TRIM_ROM_CTL_ULP; /*!< 0x00001818 CPUSS TRIM ROM CTL ULP value */
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__IOM uint32_t CPUSS_TRIM_RAM_CTL_ULP; /*!< 0x0000181C CPUSS TRIM RAM CTL ULP value */
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__IOM uint32_t CPUSS_TRIM_ROM_CTL_LP; /*!< 0x00001820 CPUSS TRIM ROM CTL LP value */
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__IOM uint32_t CPUSS_TRIM_RAM_CTL_LP; /*!< 0x00001824 CPUSS TRIM RAM CTL LP value */
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__IM uint32_t RESERVED11[502];
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__IOM uint32_t FLASH_BOOT_OBJECT_SIZE; /*!< 0x00002000 Flash Boot - Object Size */
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__IOM uint32_t FLASH_BOOT_APP_ID; /*!< 0x00002004 Flash Boot - Application ID/Version */
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__IOM uint32_t FLASH_BOOT_ATTRIBUTE; /*!< 0x00002008 N/A */
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__IOM uint32_t FLASH_BOOT_N_CORES; /*!< 0x0000200C Flash Boot - Number of Cores(N) */
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__IOM uint32_t FLASH_BOOT_VT_OFFSET; /*!< 0x00002010 Flash Boot - Core Vector Table offset */
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__IOM uint32_t FLASH_BOOT_CORE_CPUID; /*!< 0x00002014 Flash Boot - Core CPU ID/Core Index */
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__IM uint32_t RESERVED12[48];
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__IOM uint8_t FLASH_BOOT_CODE[8488]; /*!< 0x000020D8 Flash Boot - Code and Data */
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__IM uint32_t RESERVED13[1536];
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__IOM uint8_t PUBLIC_KEY[3072]; /*!< 0x00005A00 Public key for signature verification (max RSA key size 4096) */
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__IOM uint32_t BOOT_PROT_SETTINGS[384]; /*!< 0x00006600 Boot protection settings (not present in PSOC6ABLE2) */
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__IM uint32_t RESERVED14[768];
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__IOM uint32_t TOC1_OBJECT_SIZE; /*!< 0x00007800 Object size in bytes for CRC calculation starting from offset
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0x00 */
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__IOM uint32_t TOC1_MAGIC_NUMBER; /*!< 0x00007804 Magic number(0x01211219) */
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__IOM uint32_t TOC1_FHASH_OBJECTS; /*!< 0x00007808 Number of objects starting from offset 0xC to be verified for
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FACTORY_HASH */
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__IOM uint32_t TOC1_SFLASH_GENERAL_TRIM_ADDR; /*!< 0x0000780C Address of trims stored in SFLASH */
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__IOM uint32_t TOC1_UNIQUE_ID_ADDR; /*!< 0x00007810 Address of Unique ID stored in SFLASH */
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__IOM uint32_t TOC1_FB_OBJECT_ADDR; /*!< 0x00007814 Addresss of FLASH Boot(FB) object that include FLASH patch also */
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__IOM uint32_t TOC1_SYSCALL_TABLE_ADDR; /*!< 0x00007818 Address of SYSCALL_TABLE entry in SFLASH */
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__IOM uint32_t TOC1_BOOT_PROTECTION_ADDR; /*!< 0x0000781C Address of boot protection object */
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__IM uint32_t RESERVED15[119];
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__IOM uint32_t TOC1_CRC_ADDR; /*!< 0x000079FC Upper 2 bytes contain CRC16-CCITT and lower 2 bytes are 0 */
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__IOM uint32_t RTOC1_OBJECT_SIZE; /*!< 0x00007A00 Redundant Object size in bytes for CRC calculation starting
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from offset 0x00 */
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__IOM uint32_t RTOC1_MAGIC_NUMBER; /*!< 0x00007A04 Redundant Magic number(0x01211219) */
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__IOM uint32_t RTOC1_FHASH_OBJECTS; /*!< 0x00007A08 Redundant Number of objects starting from offset 0xC to be
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verified for FACTORY_HASH */
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__IOM uint32_t RTOC1_SFLASH_GENERAL_TRIM_ADDR; /*!< 0x00007A0C Redundant Address of trims stored in SFLASH */
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__IOM uint32_t RTOC1_UNIQUE_ID_ADDR; /*!< 0x00007A10 Redundant Address of Unique ID stored in SFLASH */
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__IOM uint32_t RTOC1_FB_OBJECT_ADDR; /*!< 0x00007A14 Redundant Addresss of FLASH Boot(FB) object that include FLASH
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patch also */
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__IOM uint32_t RTOC1_SYSCALL_TABLE_ADDR; /*!< 0x00007A18 Redundant Address of SYSCALL_TABLE entry in SFLASH */
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__IM uint32_t RESERVED16[120];
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__IOM uint32_t RTOC1_CRC_ADDR; /*!< 0x00007BFC Redundant CRC,Upper 2 bytes contain CRC16-CCITT and lower 2
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bytes are 0 */
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__IOM uint32_t TOC2_OBJECT_SIZE; /*!< 0x00007C00 Object size in bytes for CRC calculation starting from offset
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0x00 */
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__IOM uint32_t TOC2_MAGIC_NUMBER; /*!< 0x00007C04 Magic number(0x01211220) */
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__IOM uint32_t TOC2_KEY_BLOCK_ADDR; /*!< 0x00007C08 Address of Key Storage FLASH blocks */
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__IOM uint32_t TOC2_SMIF_CFG_STRUCT_ADDR; /*!< 0x00007C0C Null terminated table of pointers representing the SMIF
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configuration structure */
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__IOM uint32_t TOC2_FIRST_USER_APP_ADDR; /*!< 0x00007C10 Address of First User Application Object */
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__IOM uint32_t TOC2_FIRST_USER_APP_FORMAT; /*!< 0x00007C14 Format of First User Application Object. 0 - Basic, 1 - Cypress
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standard & 2 - Simplified */
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__IOM uint32_t TOC2_SECOND_USER_APP_ADDR; /*!< 0x00007C18 Address of Second User Application Object */
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__IOM uint32_t TOC2_SECOND_USER_APP_FORMAT; /*!< 0x00007C1C Format of Second User Application Object. 0 - Basic, 1 -
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Cypress standard & 2 - Simplified */
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__IOM uint32_t TOC2_SHASH_OBJECTS; /*!< 0x00007C20 Number of additional objects(in addition to objects covered by
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FACORY_CAMC) starting from offset 0x24 to be verified for
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SECURE_HASH(SHASH) */
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__IOM uint32_t TOC2_SIGNATURE_VERIF_KEY; /*!< 0x00007C24 Address of signature verification key (0 if none).The object is
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signature specific key. It is the public key in case of RSA */
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__IM uint32_t RESERVED17[116];
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__IOM uint32_t TOC2_FLAGS; /*!< 0x00007DF8 TOC2_FLAGS */
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__IOM uint32_t TOC2_CRC_ADDR; /*!< 0x00007DFC CRC,Upper 2 bytes contain CRC16-CCITT and lower 2 bytes are 0 */
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__IOM uint32_t RTOC2_OBJECT_SIZE; /*!< 0x00007E00 Redundant Object size in bytes for CRC calculation starting
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from offset 0x00 */
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__IOM uint32_t RTOC2_MAGIC_NUMBER; /*!< 0x00007E04 Redundant Magic number(0x01211220) */
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__IOM uint32_t RTOC2_KEY_BLOCK_ADDR; /*!< 0x00007E08 Redundant Address of Key Storage FLASH blocks */
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__IOM uint32_t RTOC2_SMIF_CFG_STRUCT_ADDR; /*!< 0x00007E0C Redundant Null terminated table of pointers representing the
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SMIF configuration structure */
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__IOM uint32_t RTOC2_FIRST_USER_APP_ADDR; /*!< 0x00007E10 Redundant Address of First User Application Object */
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__IOM uint32_t RTOC2_FIRST_USER_APP_FORMAT; /*!< 0x00007E14 Redundant Format of First User Application Object. 0 - Basic, 1
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- Cypress standard & 2 - Simplified */
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__IOM uint32_t RTOC2_SECOND_USER_APP_ADDR; /*!< 0x00007E18 Redundant Address of Second User Application Object */
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__IOM uint32_t RTOC2_SECOND_USER_APP_FORMAT; /*!< 0x00007E1C Redundant Format of Second User Application Object. 0 - Basic,
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1 - Cypress standard & 2 - Simplified */
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__IOM uint32_t RTOC2_SHASH_OBJECTS; /*!< 0x00007E20 Redundant Number of additional objects(in addition to objects
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covered by FACORY_CAMC) starting from offset 0x24 to be verified
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for SECURE_HASH(SHASH) */
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__IOM uint32_t RTOC2_SIGNATURE_VERIF_KEY; /*!< 0x00007E24 Redundant Address of signature verification key (0 if none).The
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object is signature specific key. It is the public key in case
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of RSA */
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__IM uint32_t RESERVED18[116];
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__IOM uint32_t RTOC2_FLAGS; /*!< 0x00007FF8 RTOC2_FLAGS */
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__IOM uint32_t RTOC2_CRC_ADDR; /*!< 0x00007FFC Redundant CRC,Upper 2 bytes contain CRC16-CCITT and lower 2
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bytes are 0 */
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} SFLASH_Type; /*!< Size = 32768 (0x8000) */
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/* SFLASH.SI_REVISION_ID */
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#define SFLASH_SI_REVISION_ID_SI_REVISION_ID_Pos 0UL
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#define SFLASH_SI_REVISION_ID_SI_REVISION_ID_Msk 0xFFUL
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/* SFLASH.SILICON_ID */
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#define SFLASH_SILICON_ID_ID_Pos 0UL
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#define SFLASH_SILICON_ID_ID_Msk 0xFFFFUL
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/* SFLASH.FAMILY_ID */
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#define SFLASH_FAMILY_ID_FAMILY_ID_Pos 0UL
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#define SFLASH_FAMILY_ID_FAMILY_ID_Msk 0xFFFFUL
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/* SFLASH.DIE_LOT */
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#define SFLASH_DIE_LOT_LOT_Pos 0UL
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#define SFLASH_DIE_LOT_LOT_Msk 0xFFUL
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/* SFLASH.DIE_WAFER */
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#define SFLASH_DIE_WAFER_WAFER_Pos 0UL
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#define SFLASH_DIE_WAFER_WAFER_Msk 0xFFUL
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/* SFLASH.DIE_X */
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#define SFLASH_DIE_X_X_Pos 0UL
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#define SFLASH_DIE_X_X_Msk 0xFFUL
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/* SFLASH.DIE_Y */
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#define SFLASH_DIE_Y_Y_Pos 0UL
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#define SFLASH_DIE_Y_Y_Msk 0xFFUL
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/* SFLASH.DIE_SORT */
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#define SFLASH_DIE_SORT_S1_PASS_Pos 0UL
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#define SFLASH_DIE_SORT_S1_PASS_Msk 0x1UL
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#define SFLASH_DIE_SORT_S2_PASS_Pos 1UL
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#define SFLASH_DIE_SORT_S2_PASS_Msk 0x2UL
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#define SFLASH_DIE_SORT_S3_PASS_Pos 2UL
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#define SFLASH_DIE_SORT_S3_PASS_Msk 0x4UL
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#define SFLASH_DIE_SORT_CRI_PASS_Pos 3UL
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#define SFLASH_DIE_SORT_CRI_PASS_Msk 0x8UL
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#define SFLASH_DIE_SORT_CHI_PASS_Pos 4UL
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#define SFLASH_DIE_SORT_CHI_PASS_Msk 0x10UL
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#define SFLASH_DIE_SORT_ENG_PASS_Pos 5UL
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#define SFLASH_DIE_SORT_ENG_PASS_Msk 0x20UL
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/* SFLASH.DIE_MINOR */
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#define SFLASH_DIE_MINOR_MINOR_Pos 0UL
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#define SFLASH_DIE_MINOR_MINOR_Msk 0xFFUL
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/* SFLASH.DIE_DAY */
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#define SFLASH_DIE_DAY_MINOR_Pos 0UL
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#define SFLASH_DIE_DAY_MINOR_Msk 0xFFUL
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/* SFLASH.DIE_MONTH */
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#define SFLASH_DIE_MONTH_MINOR_Pos 0UL
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#define SFLASH_DIE_MONTH_MINOR_Msk 0xFFUL
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/* SFLASH.DIE_YEAR */
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#define SFLASH_DIE_YEAR_MINOR_Pos 0UL
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#define SFLASH_DIE_YEAR_MINOR_Msk 0xFFUL
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/* SFLASH.SAR_TEMP_MULTIPLIER */
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#define SFLASH_SAR_TEMP_MULTIPLIER_TEMP_MULTIPLIER_Pos 0UL
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#define SFLASH_SAR_TEMP_MULTIPLIER_TEMP_MULTIPLIER_Msk 0xFFFFUL
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/* SFLASH.SAR_TEMP_OFFSET */
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#define SFLASH_SAR_TEMP_OFFSET_TEMP_OFFSET_Pos 0UL
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#define SFLASH_SAR_TEMP_OFFSET_TEMP_OFFSET_Msk 0xFFFFUL
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/* SFLASH.CSP_PANEL_ID */
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#define SFLASH_CSP_PANEL_ID_DATA32_Pos 0UL
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#define SFLASH_CSP_PANEL_ID_DATA32_Msk 0xFFFFFFFFUL
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/* SFLASH.LDO_0P9V_TRIM */
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#define SFLASH_LDO_0P9V_TRIM_DATA8_Pos 0UL
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#define SFLASH_LDO_0P9V_TRIM_DATA8_Msk 0xFFUL
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/* SFLASH.LDO_1P1V_TRIM */
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#define SFLASH_LDO_1P1V_TRIM_DATA8_Pos 0UL
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#define SFLASH_LDO_1P1V_TRIM_DATA8_Msk 0xFFUL
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/* SFLASH.BLE_DEVICE_ADDRESS */
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#define SFLASH_BLE_DEVICE_ADDRESS_ADDR_Pos 0UL
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#define SFLASH_BLE_DEVICE_ADDRESS_ADDR_Msk 0xFFFFFFFFUL
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/* SFLASH.USER_FREE_ROW1 */
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#define SFLASH_USER_FREE_ROW1_DATA32_Pos 0UL
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#define SFLASH_USER_FREE_ROW1_DATA32_Msk 0xFFFFFFFFUL
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/* SFLASH.USER_FREE_ROW2 */
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#define SFLASH_USER_FREE_ROW2_DATA32_Pos 0UL
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#define SFLASH_USER_FREE_ROW2_DATA32_Msk 0xFFFFFFFFUL
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/* SFLASH.USER_FREE_ROW3 */
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#define SFLASH_USER_FREE_ROW3_DATA32_Pos 0UL
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#define SFLASH_USER_FREE_ROW3_DATA32_Msk 0xFFFFFFFFUL
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/* SFLASH.DEVICE_UID */
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#define SFLASH_DEVICE_UID_DATA8_Pos 0UL
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#define SFLASH_DEVICE_UID_DATA8_Msk 0xFFUL
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/* SFLASH.MASTER_KEY */
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#define SFLASH_MASTER_KEY_DATA8_Pos 0UL
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#define SFLASH_MASTER_KEY_DATA8_Msk 0xFFUL
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/* SFLASH.STANDARD_SMPU_STRUCT_SLAVE_ADDR */
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#define SFLASH_STANDARD_SMPU_STRUCT_SLAVE_ADDR_DATA32_Pos 0UL
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#define SFLASH_STANDARD_SMPU_STRUCT_SLAVE_ADDR_DATA32_Msk 0xFFFFFFFFUL
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/* SFLASH.STANDARD_SMPU_STRUCT_SLAVE_ATTR */
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#define SFLASH_STANDARD_SMPU_STRUCT_SLAVE_ATTR_DATA32_Pos 0UL
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#define SFLASH_STANDARD_SMPU_STRUCT_SLAVE_ATTR_DATA32_Msk 0xFFFFFFFFUL
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/* SFLASH.STANDARD_SMPU_STRUCT_MASTER_ATTR */
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#define SFLASH_STANDARD_SMPU_STRUCT_MASTER_ATTR_DATA32_Pos 0UL
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#define SFLASH_STANDARD_SMPU_STRUCT_MASTER_ATTR_DATA32_Msk 0xFFFFFFFFUL
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/* SFLASH.STANDARD_MPU_STRUCT */
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#define SFLASH_STANDARD_MPU_STRUCT_DATA32_Pos 0UL
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#define SFLASH_STANDARD_MPU_STRUCT_DATA32_Msk 0xFFFFFFFFUL
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/* SFLASH.STANDARD_PPU_STRUCT */
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#define SFLASH_STANDARD_PPU_STRUCT_DATA32_Pos 0UL
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#define SFLASH_STANDARD_PPU_STRUCT_DATA32_Msk 0xFFFFFFFFUL
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/* SFLASH.PILO_FREQ_STEP */
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#define SFLASH_PILO_FREQ_STEP_STEP_Pos 0UL
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#define SFLASH_PILO_FREQ_STEP_STEP_Msk 0xFFFFUL
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/* SFLASH.CSDV2_CSD0_ADC_VREF0 */
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#define SFLASH_CSDV2_CSD0_ADC_VREF0_VREF_HI_LEVELS_1P2_Pos 0UL
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#define SFLASH_CSDV2_CSD0_ADC_VREF0_VREF_HI_LEVELS_1P2_Msk 0xFFFFUL
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#define SFLASH_CSDV2_CSD0_ADC_VREF0_VREF_HI_LEVELS_1P6_Pos 16UL
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#define SFLASH_CSDV2_CSD0_ADC_VREF0_VREF_HI_LEVELS_1P6_Msk 0xFFFF0000UL
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/* SFLASH.CSDV2_CSD0_ADC_VREF1 */
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#define SFLASH_CSDV2_CSD0_ADC_VREF1_VREF_HI_LEVELS_2P1_Pos 0UL
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#define SFLASH_CSDV2_CSD0_ADC_VREF1_VREF_HI_LEVELS_2P1_Msk 0xFFFFUL
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#define SFLASH_CSDV2_CSD0_ADC_VREF1_VREF_HI_LEVELS_0P8_Pos 16UL
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#define SFLASH_CSDV2_CSD0_ADC_VREF1_VREF_HI_LEVELS_0P8_Msk 0xFFFF0000UL
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/* SFLASH.CSDV2_CSD0_ADC_VREF2 */
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#define SFLASH_CSDV2_CSD0_ADC_VREF2_VREF_HI_LEVELS_2P6_Pos 0UL
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#define SFLASH_CSDV2_CSD0_ADC_VREF2_VREF_HI_LEVELS_2P6_Msk 0xFFFFUL
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/* SFLASH.PWR_TRIM_WAKE_CTL */
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#define SFLASH_PWR_TRIM_WAKE_CTL_WAKE_DELAY_Pos 0UL
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#define SFLASH_PWR_TRIM_WAKE_CTL_WAKE_DELAY_Msk 0xFFUL
|
|
/* SFLASH.RADIO_LDO_TRIMS */
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#define SFLASH_RADIO_LDO_TRIMS_LDO_ACT_Pos 0UL
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#define SFLASH_RADIO_LDO_TRIMS_LDO_ACT_Msk 0xFUL
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#define SFLASH_RADIO_LDO_TRIMS_LDO_LNA_Pos 4UL
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#define SFLASH_RADIO_LDO_TRIMS_LDO_LNA_Msk 0x30UL
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#define SFLASH_RADIO_LDO_TRIMS_LDO_IF_Pos 6UL
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|
#define SFLASH_RADIO_LDO_TRIMS_LDO_IF_Msk 0xC0UL
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#define SFLASH_RADIO_LDO_TRIMS_LDO_DIG_Pos 8UL
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#define SFLASH_RADIO_LDO_TRIMS_LDO_DIG_Msk 0x300UL
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|
/* SFLASH.CPUSS_TRIM_ROM_CTL_ULP */
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#define SFLASH_CPUSS_TRIM_ROM_CTL_ULP_DATA32_Pos 0UL
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#define SFLASH_CPUSS_TRIM_ROM_CTL_ULP_DATA32_Msk 0xFFFFFFFFUL
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|
/* SFLASH.CPUSS_TRIM_RAM_CTL_ULP */
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#define SFLASH_CPUSS_TRIM_RAM_CTL_ULP_DATA32_Pos 0UL
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#define SFLASH_CPUSS_TRIM_RAM_CTL_ULP_DATA32_Msk 0xFFFFFFFFUL
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|
/* SFLASH.CPUSS_TRIM_ROM_CTL_LP */
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#define SFLASH_CPUSS_TRIM_ROM_CTL_LP_DATA32_Pos 0UL
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#define SFLASH_CPUSS_TRIM_ROM_CTL_LP_DATA32_Msk 0xFFFFFFFFUL
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|
/* SFLASH.CPUSS_TRIM_RAM_CTL_LP */
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#define SFLASH_CPUSS_TRIM_RAM_CTL_LP_DATA32_Pos 0UL
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#define SFLASH_CPUSS_TRIM_RAM_CTL_LP_DATA32_Msk 0xFFFFFFFFUL
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|
/* SFLASH.FLASH_BOOT_OBJECT_SIZE */
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|
#define SFLASH_FLASH_BOOT_OBJECT_SIZE_DATA32_Pos 0UL
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|
#define SFLASH_FLASH_BOOT_OBJECT_SIZE_DATA32_Msk 0xFFFFFFFFUL
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|
/* SFLASH.FLASH_BOOT_APP_ID */
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|
#define SFLASH_FLASH_BOOT_APP_ID_APP_ID_Pos 0UL
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|
#define SFLASH_FLASH_BOOT_APP_ID_APP_ID_Msk 0xFFFFUL
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|
#define SFLASH_FLASH_BOOT_APP_ID_MINOR_VERSION_Pos 16UL
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|
#define SFLASH_FLASH_BOOT_APP_ID_MINOR_VERSION_Msk 0xFF0000UL
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|
#define SFLASH_FLASH_BOOT_APP_ID_MAJOR_VERSION_Pos 24UL
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|
#define SFLASH_FLASH_BOOT_APP_ID_MAJOR_VERSION_Msk 0xF000000UL
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|
/* SFLASH.FLASH_BOOT_ATTRIBUTE */
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#define SFLASH_FLASH_BOOT_ATTRIBUTE_DATA32_Pos 0UL
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|
#define SFLASH_FLASH_BOOT_ATTRIBUTE_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.FLASH_BOOT_N_CORES */
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|
#define SFLASH_FLASH_BOOT_N_CORES_DATA32_Pos 0UL
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|
#define SFLASH_FLASH_BOOT_N_CORES_DATA32_Msk 0xFFFFFFFFUL
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|
/* SFLASH.FLASH_BOOT_VT_OFFSET */
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|
#define SFLASH_FLASH_BOOT_VT_OFFSET_DATA32_Pos 0UL
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|
#define SFLASH_FLASH_BOOT_VT_OFFSET_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.FLASH_BOOT_CORE_CPUID */
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|
#define SFLASH_FLASH_BOOT_CORE_CPUID_DATA32_Pos 0UL
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|
#define SFLASH_FLASH_BOOT_CORE_CPUID_DATA32_Msk 0xFFFFFFFFUL
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|
/* SFLASH.FLASH_BOOT_CODE */
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|
#define SFLASH_FLASH_BOOT_CODE_DATA32_Pos 0UL
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|
#define SFLASH_FLASH_BOOT_CODE_DATA32_Msk 0xFFFFFFFFUL
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|
/* SFLASH.PUBLIC_KEY */
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|
#define SFLASH_PUBLIC_KEY_DATA_Pos 0UL
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|
#define SFLASH_PUBLIC_KEY_DATA_Msk 0xFFUL
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|
/* SFLASH.BOOT_PROT_SETTINGS */
|
|
#define SFLASH_BOOT_PROT_SETTINGS_DATA32_Pos 0UL
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|
#define SFLASH_BOOT_PROT_SETTINGS_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.TOC1_OBJECT_SIZE */
|
|
#define SFLASH_TOC1_OBJECT_SIZE_DATA32_Pos 0UL
|
|
#define SFLASH_TOC1_OBJECT_SIZE_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.TOC1_MAGIC_NUMBER */
|
|
#define SFLASH_TOC1_MAGIC_NUMBER_DATA32_Pos 0UL
|
|
#define SFLASH_TOC1_MAGIC_NUMBER_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.TOC1_FHASH_OBJECTS */
|
|
#define SFLASH_TOC1_FHASH_OBJECTS_DATA32_Pos 0UL
|
|
#define SFLASH_TOC1_FHASH_OBJECTS_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.TOC1_SFLASH_GENERAL_TRIM_ADDR */
|
|
#define SFLASH_TOC1_SFLASH_GENERAL_TRIM_ADDR_DATA32_Pos 0UL
|
|
#define SFLASH_TOC1_SFLASH_GENERAL_TRIM_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.TOC1_UNIQUE_ID_ADDR */
|
|
#define SFLASH_TOC1_UNIQUE_ID_ADDR_DATA32_Pos 0UL
|
|
#define SFLASH_TOC1_UNIQUE_ID_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.TOC1_FB_OBJECT_ADDR */
|
|
#define SFLASH_TOC1_FB_OBJECT_ADDR_DATA32_Pos 0UL
|
|
#define SFLASH_TOC1_FB_OBJECT_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.TOC1_SYSCALL_TABLE_ADDR */
|
|
#define SFLASH_TOC1_SYSCALL_TABLE_ADDR_DATA32_Pos 0UL
|
|
#define SFLASH_TOC1_SYSCALL_TABLE_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.TOC1_BOOT_PROTECTION_ADDR */
|
|
#define SFLASH_TOC1_BOOT_PROTECTION_ADDR_DATA32_Pos 0UL
|
|
#define SFLASH_TOC1_BOOT_PROTECTION_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.TOC1_CRC_ADDR */
|
|
#define SFLASH_TOC1_CRC_ADDR_DATA32_Pos 0UL
|
|
#define SFLASH_TOC1_CRC_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.RTOC1_OBJECT_SIZE */
|
|
#define SFLASH_RTOC1_OBJECT_SIZE_DATA32_Pos 0UL
|
|
#define SFLASH_RTOC1_OBJECT_SIZE_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.RTOC1_MAGIC_NUMBER */
|
|
#define SFLASH_RTOC1_MAGIC_NUMBER_DATA32_Pos 0UL
|
|
#define SFLASH_RTOC1_MAGIC_NUMBER_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.RTOC1_FHASH_OBJECTS */
|
|
#define SFLASH_RTOC1_FHASH_OBJECTS_DATA32_Pos 0UL
|
|
#define SFLASH_RTOC1_FHASH_OBJECTS_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.RTOC1_SFLASH_GENERAL_TRIM_ADDR */
|
|
#define SFLASH_RTOC1_SFLASH_GENERAL_TRIM_ADDR_DATA32_Pos 0UL
|
|
#define SFLASH_RTOC1_SFLASH_GENERAL_TRIM_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.RTOC1_UNIQUE_ID_ADDR */
|
|
#define SFLASH_RTOC1_UNIQUE_ID_ADDR_DATA32_Pos 0UL
|
|
#define SFLASH_RTOC1_UNIQUE_ID_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.RTOC1_FB_OBJECT_ADDR */
|
|
#define SFLASH_RTOC1_FB_OBJECT_ADDR_DATA32_Pos 0UL
|
|
#define SFLASH_RTOC1_FB_OBJECT_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.RTOC1_SYSCALL_TABLE_ADDR */
|
|
#define SFLASH_RTOC1_SYSCALL_TABLE_ADDR_DATA32_Pos 0UL
|
|
#define SFLASH_RTOC1_SYSCALL_TABLE_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.RTOC1_CRC_ADDR */
|
|
#define SFLASH_RTOC1_CRC_ADDR_DATA32_Pos 0UL
|
|
#define SFLASH_RTOC1_CRC_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.TOC2_OBJECT_SIZE */
|
|
#define SFLASH_TOC2_OBJECT_SIZE_DATA32_Pos 0UL
|
|
#define SFLASH_TOC2_OBJECT_SIZE_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.TOC2_MAGIC_NUMBER */
|
|
#define SFLASH_TOC2_MAGIC_NUMBER_DATA32_Pos 0UL
|
|
#define SFLASH_TOC2_MAGIC_NUMBER_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.TOC2_KEY_BLOCK_ADDR */
|
|
#define SFLASH_TOC2_KEY_BLOCK_ADDR_DATA32_Pos 0UL
|
|
#define SFLASH_TOC2_KEY_BLOCK_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.TOC2_SMIF_CFG_STRUCT_ADDR */
|
|
#define SFLASH_TOC2_SMIF_CFG_STRUCT_ADDR_DATA32_Pos 0UL
|
|
#define SFLASH_TOC2_SMIF_CFG_STRUCT_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.TOC2_FIRST_USER_APP_ADDR */
|
|
#define SFLASH_TOC2_FIRST_USER_APP_ADDR_DATA32_Pos 0UL
|
|
#define SFLASH_TOC2_FIRST_USER_APP_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.TOC2_FIRST_USER_APP_FORMAT */
|
|
#define SFLASH_TOC2_FIRST_USER_APP_FORMAT_DATA32_Pos 0UL
|
|
#define SFLASH_TOC2_FIRST_USER_APP_FORMAT_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.TOC2_SECOND_USER_APP_ADDR */
|
|
#define SFLASH_TOC2_SECOND_USER_APP_ADDR_DATA32_Pos 0UL
|
|
#define SFLASH_TOC2_SECOND_USER_APP_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.TOC2_SECOND_USER_APP_FORMAT */
|
|
#define SFLASH_TOC2_SECOND_USER_APP_FORMAT_DATA32_Pos 0UL
|
|
#define SFLASH_TOC2_SECOND_USER_APP_FORMAT_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.TOC2_SHASH_OBJECTS */
|
|
#define SFLASH_TOC2_SHASH_OBJECTS_DATA32_Pos 0UL
|
|
#define SFLASH_TOC2_SHASH_OBJECTS_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.TOC2_SIGNATURE_VERIF_KEY */
|
|
#define SFLASH_TOC2_SIGNATURE_VERIF_KEY_DATA32_Pos 0UL
|
|
#define SFLASH_TOC2_SIGNATURE_VERIF_KEY_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.TOC2_FLAGS */
|
|
#define SFLASH_TOC2_FLAGS_DATA32_Pos 0UL
|
|
#define SFLASH_TOC2_FLAGS_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.TOC2_CRC_ADDR */
|
|
#define SFLASH_TOC2_CRC_ADDR_DATA32_Pos 0UL
|
|
#define SFLASH_TOC2_CRC_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.RTOC2_OBJECT_SIZE */
|
|
#define SFLASH_RTOC2_OBJECT_SIZE_DATA32_Pos 0UL
|
|
#define SFLASH_RTOC2_OBJECT_SIZE_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.RTOC2_MAGIC_NUMBER */
|
|
#define SFLASH_RTOC2_MAGIC_NUMBER_DATA32_Pos 0UL
|
|
#define SFLASH_RTOC2_MAGIC_NUMBER_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.RTOC2_KEY_BLOCK_ADDR */
|
|
#define SFLASH_RTOC2_KEY_BLOCK_ADDR_DATA32_Pos 0UL
|
|
#define SFLASH_RTOC2_KEY_BLOCK_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.RTOC2_SMIF_CFG_STRUCT_ADDR */
|
|
#define SFLASH_RTOC2_SMIF_CFG_STRUCT_ADDR_DATA32_Pos 0UL
|
|
#define SFLASH_RTOC2_SMIF_CFG_STRUCT_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.RTOC2_FIRST_USER_APP_ADDR */
|
|
#define SFLASH_RTOC2_FIRST_USER_APP_ADDR_DATA32_Pos 0UL
|
|
#define SFLASH_RTOC2_FIRST_USER_APP_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.RTOC2_FIRST_USER_APP_FORMAT */
|
|
#define SFLASH_RTOC2_FIRST_USER_APP_FORMAT_DATA32_Pos 0UL
|
|
#define SFLASH_RTOC2_FIRST_USER_APP_FORMAT_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.RTOC2_SECOND_USER_APP_ADDR */
|
|
#define SFLASH_RTOC2_SECOND_USER_APP_ADDR_DATA32_Pos 0UL
|
|
#define SFLASH_RTOC2_SECOND_USER_APP_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.RTOC2_SECOND_USER_APP_FORMAT */
|
|
#define SFLASH_RTOC2_SECOND_USER_APP_FORMAT_DATA32_Pos 0UL
|
|
#define SFLASH_RTOC2_SECOND_USER_APP_FORMAT_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.RTOC2_SHASH_OBJECTS */
|
|
#define SFLASH_RTOC2_SHASH_OBJECTS_DATA32_Pos 0UL
|
|
#define SFLASH_RTOC2_SHASH_OBJECTS_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.RTOC2_SIGNATURE_VERIF_KEY */
|
|
#define SFLASH_RTOC2_SIGNATURE_VERIF_KEY_DATA32_Pos 0UL
|
|
#define SFLASH_RTOC2_SIGNATURE_VERIF_KEY_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.RTOC2_FLAGS */
|
|
#define SFLASH_RTOC2_FLAGS_DATA32_Pos 0UL
|
|
#define SFLASH_RTOC2_FLAGS_DATA32_Msk 0xFFFFFFFFUL
|
|
/* SFLASH.RTOC2_CRC_ADDR */
|
|
#define SFLASH_RTOC2_CRC_ADDR_DATA32_Pos 0UL
|
|
#define SFLASH_RTOC2_CRC_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
|
|
|
|
|
#endif /* _CYIP_SFLASH_H_ */
|
|
|
|
|
|
/* [] END OF FILE */
|